A semiconductor device includes a first semiconductor chip that includes a first conductive pad whose top surface is exposed; and a second semiconductor chip that includes a second conductive pad whose top surface is exposed and in contact with at least a portion of the top surface of the first conductive pad. The first semiconductor chip may include a first diffusion barrier in contact with a bottom surface of the first conductive pad, and a second diffusion barrier in contact with a lateral surface of the first conductive pad, and the first diffusion barrier and the second diffusion barrier may include different materials from each other.

A via for semiconductor devices is disclosed. Implementations of vias for semiconductor devices may include: a semiconductor substrate that includes a first side; a via extending from the first side of the semiconductor substrate to a pad; a polymer layer coupled along an entire sidewall of the via, the polymer layer in direct contact with the pad; and a metal layer directly coupled over the polymer layer and directly coupled with the pad.

The present application provides a semiconductor device. The semiconductor device includes a bonding pad disposed over a semiconductor substrate; a first spacer disposed over a top surface of the bonding pad; a second spacer disposed over a sidewall of the bonding pad; a dielectric layer between the bonding pad and the semiconductor substrate. The dielectric layer includes silicon-rich oxide; and a conductive bump disposed over the first passivation layer. The conductive bump is electrically connected to a source/drain (S/D) region in the semiconductor substrate through the bonding pad. The semiconductor device also includes a dielectric liner disposed between the first spacer and the bonding pad; and a first passivation layer covering the second spacer, wherein the dielectric liner is L-shaped, and the first spacer is separated from the bonding pad by the dielectric liner.

A method includes forming a first conductive feature, depositing a passivation layer on a sidewall and a top surface of the first conductive feature, etching the passivation layer to reveal the first conductive feature, and recessing a first top surface of the passivation layer to form a step. The step comprises a second top surface of the passivation layer. The method further includes forming a planarization layer on the passivation layer, and forming a second conductive feature extending into the passivation layer to contact the first conductive feature.

A method includes forming a metal seed layer over a first conductive feature of a wafer, forming a patterned photo resist on the metal seed layer, forming a second conductive feature in an opening in the patterned photo resist, and heating the wafer to generate a gap between the second conductive feature and the patterned photo resist. A protection layer is plated on the second conductive feature. The method further includes removing the patterned photo resist, and etching the metal seed layer.

The present disclosure provides an integrated circuit (IC) structure. The IC structure includes a semiconductor substrate; an interconnection structure formed on the semiconductor substrate; and a redistribution layer (RDL) metallic feature formed on the interconnection structure. The RDL metallic feature further includes a barrier layer disposed on the interconnection structure; a diffusion layer disposed on the barrier layer, wherein the diffusion layer includes metal and oxygen; and a metallic layer disposed on the diffusion layer.

A semiconductor device of an embodiment includes a first chip having a memory cell array, and a second chip having a control circuit. The first chip includes a substrate, a pad, a first structural body, and a second structural body. The substrate is arranged on the side opposite to a joined face of the first chip joined to the second chip, and includes a first face, a second face, and an opening extending from the second face to the first face in a first region. The memory cell array is provided between the first face and the opposed joined face. The pad is provided in the opening. The first structural body is provided between the first face and the joined face, and is electrically connected to the pad. The second structural body is provided between the first face and the joined face in the first region.

A semiconductor memory device includes: a stack above a peripheral circuit on a first substrate, in which first conductive layers and first insulation layers are alternately stacked in a first direction each; a first pillar through the stack, in which a semiconductor layer and each first conductive layer form a memory cell at their intersection; a second substrate including a first region above the stack and the first pillar, being connected to a semiconductor layer, and a second region juxtaposed with the first region in a second direction; a second insulation layer through the second substrate, insulating the regions from each other; and a second conductive layer including a first portion through the second substrate, and a second portion extending in the second direction above the second substrate and including a part defining a bonding pad. The second portion overlaps with the second insulation layer in the first direction.

According to an aspect of the inventive concept, there is provided a die-to-wafer bonding structure including a die having a first test pad, a first bonding pad formed on the first test pad, and a first insulating layer, the first bonding pad penetrates the first insulating layer. The structure may further include a wafer having a second test pad, a second bonding pad formed on the second test pad, and a second insulating layer, the second bonding pad penetrates the second insulating layer. The structure may further include a polymer layer surrounding all side surfaces of the first bonding pad and all side surfaces of the second bonding pad, the polymer layer being arranged between the die and the wafer. Additionally, the wafer and the die may be bonded together.

A microelectronic device has bump bonds and an inductor on a die. The microelectronic device includes first lateral conductors extending along a terminal surface of the die, wherein at least some of the first lateral conductors contact at least some of terminals of the die. The microelectronic device also includes conductive columns on the first lateral conductors, extending perpendicularly from the terminal surface, and second lateral conductors on the conductive columns, opposite from the first lateral conductors, extending laterally in a plane parallel to the terminal surface. A first set of the first lateral conductors, the conductive columns, and the second lateral conductors provide the bump bonds of the microelectronic device. A second set of the first lateral conductors, the conductive columns, and the second lateral conductors are electrically coupled in series to form the inductor. Methods of forming the microelectronic device are also disclosed.