Device and method for forming a device are presented. A substrate having circuit component and a back-end-of-line (BEOL) dielectric layer with interconnects is provided. A pad dielectric layer is formed over the BEOL dielectric layer. The pad dielectric layer includes a pad via opening which exposes a surface of one of the interconnects in the BEOL dielectric layer. A pad interconnect is formed on the pad dielectric layer and the pad interconnect is coupled to one of the interconnect in the BEOL dielectric by a pad via contact in the pad via opening. The pad interconnect comprises a pad interconnect pattern which is devoid of 90° angles and any angled structures contained in the pad interconnect pattern less than 90°. A passivation layer is formed on the substrate. The passivation layer lines the pad interconnect and covers an exposed surface of the pad dielectric layer.

A semiconductor device and a fabricating method thereof are provided. The semiconductor device includes a semiconductor structure and an input/output pad. The semiconductor structure includes a first substrate and a conductive layer, in which the first substrate has a first surface and a second surface opposite to each other, the conductive layer is disposed on the first surface of the first substrate, and the conductive layer includes one or more first trace. The first semiconductor structure has a recess penetrating the first substrate and exposing the one or more first trace, and the input/output pad is disposed on the one or more first trace and in the recess.

This disclosure relates generally to a wafer having a plurality of semiconductor chips having a major surface, a metal contact positioned on one of the plurality of semiconductor chips and having a side surface and contact surface, the contact surface substantially parallel to the major surface, wherein the contact surface defines a thickness of the metal contact relative to the major surface, an underfill layer abutting the one of the plurality of semiconductor chips and the side surface of the metal contact, the underfill layer having a top surface substantially parallel to the major surface, wherein the top surface of the underfill layer defines a thickness of the underfill layer relative to the major surface, the thickness of the underfill layer being not greater than the thickness of the metal contact, and a solder bump formed in electrical contact with the contact surface of the metal contact.

An apparatus relating generally to a substrate is disclosed. In such an apparatus, a first bond via array has first wires extending from a surface of the substrate. A second bond via array has second wires extending from the surface of the substrate. The first bond via array is disposed at least partially within the second bond via array. The first wires of the first bond via array are of a first height. The second wires of the second bond via array are of a second height greater than the first height for coupling of at least one die to the first bond via array at least partially disposed within the second bond via array.

A multi-chip package structure includes a first chip, a second chip, a circuit layer, a plurality of first conductive bumps, a plurality of second conductive bumps and an underfill. The first chip has a chip bonding region, a plurality of first inner pads and first outer pads. The circuit layer is disposed on the first chip and includes a plurality of insulating layers and at least one metal layer. The insulating layers have a groove disposed between the first inner pads and the first outer pads and surrounding the first inner pads. The first conductive bumps are disposed on the first outer pads. The second chip is flipped on the chip bonding region. Each first inner pad is electrically connected to a second pad of the second chip through the second conductive bump. The underfill is disposed between the first and second chips and covers the second conductive bumps.

Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a method includes forming a contact pad over a semiconductor device. A passivation material is formed over the contact pad. The passivation material has a thickness and is a type of material such that an electrical connection may be made to the contact pad through the passivation material.

A method of fabricating a semiconductor structure includes: forming a conductive layer on a first insulating layer; etching a portion of the conductive layer to expose a portion of the first insulating layer; deforming a surface of the portion of the first insulating layer to form a rough surface of the first insulating layer; and removing a residue of the conductive layer on the rough surface of the first insulating layer.

An interconnection structure and method disclosed for providing an interconnection structure that includes conductive features having reduced topographic variations. The interconnection structure includes a contact pad disposed over a substrate. The contact pad includes a first layer of a first conductive material and a second layer of a second conductive material over the first layer. The first conductive material and the second conductive material are made of substantially the same material and have a first average grain size and a second average grain size that is smaller than the first average grain size. The interconnection structure also includes a passivation layer covering the substrate and the contact pad, and the passivation layer has an opening exposing the contact pad.

A semiconductor device includes: a semiconductor layer formed on a substrate; a first resin layer formed on the semiconductor layer; a second resin layer formed on the first resin layer; a first wiring layer that is formed on the semiconductor layer and is buried in the second resin layer; a second wiring layer that is formed on the second resin layer and the first wiring layer, and is electrically connected to the first wiring layer; and a first inorganic insulating film covering the second resin layer and the second wiring layer, wherein an area of the first wiring layer is larger than an area of the second wiring layer.

A semiconductor device has a semiconductor wafer and a conductive via formed partially through the semiconductor wafer. A portion of the semiconductor wafer and conductive via is removed by a chemical mechanical polishing process. The semiconductor wafer and conductive via are coplanar at first and second surfaces. A first insulating layer and a second insulating layer are formed over the conductive via and semiconductor wafer. The first insulating layer includes an inorganic material and the second insulating layer includes an organic material. An opening in the first and second insulating layers is formed over the conductive via while a second portion of the conductive via remains covered by the first and second insulating layers. A conductive layer is formed over the conductive via and first insulating layer. An interconnect structure is formed over the conductive layer. The semiconductor wafer is singulated into individual semiconductor die.