A method of forming a metal-insulator-metal (MIM) capacitor with copper top and bottom plates may begin with a copper interconnect layer (e.g., Cu MTOP) including a copper structure defining the capacitor bottom plate. A passivation region is formed over the bottom plate, and a wide top plate opening is etched in the passivation region, to expose the bottom plate. A dielectric layer is deposited into the top plate opening and onto the exposed bottom plate. Narrow via opening(s) are then etched in the passivation region. The wide top plate opening and narrow via opening(s) are concurrently filled with copper to define a copper top plate and copper via(s) in contact with the bottom plate. A first aluminum bond pad is formed on the copper top plate, and a second aluminum bond pad is formed in contact with the copper via(s) to provide a conductive coupling to the bottom plate.

A solid-state imaging device capable of achieving a further decrease in size such as a further decrease in height, a further increase in speed of wiring, and a further increase in density of wiring is to be provided.

A solid-state imaging device to be provided includes: a first semiconductor device including a semiconductor layer in which a photoelectric conversion unit that photoelectrically converts incident light and a penetrating via are provided, a first connecting portion and a second connecting portion on the surface side of the semiconductor layer on the side that receives the light, and a connecting wiring line that connects the first connecting portion, the second connecting portion, and the penetrating via; and a second semiconductor device that is mounted on the first semiconductor device with the first connecting portion. The solid-state imaging device is connected to an external terminal by the second connecting portion.

The present disclosure is directed to a wafer level chip scale package (WLCSP) with various combinations of contacts and Under Bump Metallizations (UBMs) having different structures and different amounts solder coupled to the contacts and UBMs. Although the contacts have different structures and the volume of solder differs, the total standoff height along the WLCSP remains substantially the same. Each portion of solder coupled to each respective contact and UBM includes a point furthest away from an active surface of a die of the WLCSP. Each point of each respective portion of solder is co-planar with each other respective point of the other respective portions of solder. Additionally, the contacts with various and different structures are positioned accordingly on the active surface of the die of the WLCSP to reduce failures that may result from the WLCSP being exposed to thermal cycling or the WLCSP being dropped.

The present disclosure is directed to a wafer level chip scale package (WLCSP) with various combinations of contacts and Under Bump Metallizations (UBMs) having different structures and different amounts solder coupled to the contacts and UBMs. Although the contacts have different structures and the volume of solder differs, the total standoff height along the WLCSP remains substantially the same. Each portion of solder coupled to each respective contact and UBM includes a point furthest away from an active surface of a die of the WLCSP. Each point of each respective portion of solder is co-planar with each other respective point of the other respective portions of solder. Additionally, the contacts with various and different structures are positioned accordingly on the active surface of the die of the WLCSP to reduce failures that may result from the WLCSP being exposed to thermal cycling or the WLCSP being dropped.

A method of forming a metal-insulator-metal (MIM) capacitor with copper top and bottom plates may begin with a copper interconnect layer (e.g., Cu MTOP) including a copper structure defining the capacitor bottom plate. A passivation region is formed over the bottom plate, and a wide top plate opening is etched in the passivation region, to expose the bottom plate. A dielectric layer is deposited into the top plate opening and onto the exposed bottom plate. Narrow via opening(s) are then etched in the passivation region. The wide top plate opening and narrow via opening(s) are concurrently filled with copper to define a copper top plate and copper via(s) in contact with the bottom plate. A first aluminum bond pad is formed on the copper top plate, and a second aluminum bond pad is formed in contact with the copper via(s) to provide a conductive coupling to the bottom plate.

A method of forming a metal-insulator-metal (MIM) capacitor with copper top and bottom plates may begin with a copper interconnect layer (e.g., Cu MTOP) including a copper structure defining the capacitor bottom plate. A passivation region is formed over the bottom plate, and a wide top plate opening is etched in the passivation region, to expose the bottom plate. A dielectric layer is deposited into the top plate opening and onto the exposed bottom plate. Narrow via opening(s) are then etched in the passivation region. The wide top plate opening and narrow via opening(s) are concurrently filled with copper to define a copper top plate and copper via(s) in contact with the bottom plate. A first aluminum bond pad is formed on the copper top plate, and a second aluminum bond pad is formed in contact with the copper via(s) to provide a conductive coupling to the bottom plate.

This semiconductor device is provided with: a semiconductor layer; a cell that is provided on the semiconductor layer; an insulating film that covers the cell; a main electrode part that is superposed on the insulating film; a temperature-sensitive diode for sensing temperatures, the diode having a first electrode and a second electrode; and a connection electrode for diode, the connection electrode being used for the purpose of connecting the first electrode to the outside. The main electrode part has: a first bonding region to which a first conductive member is bonded; and a second bonding region to which a second conductive member is bonded. When viewed from the thickness direction of the semiconductor layer, the cell is provided on both a first semiconductor region in the semiconductor layer, and a second semiconductor region in the semiconductor layer.

Provided is a die stack structure including a first die, a second die, a first bonding structure, and a second bonding structure. The first bonding structure is disposed on a back side of the first die. The second bonding structure is disposed on a front side of the second die. The first die and the second die are bonded together via the first bonding structure and the second bonding structure and a bondable topography variation of a surface of the first bonding structure bonding with the second bonding structure is less than less than 1 m per 1 mm range. A method of manufacturing the die stack structure is also provided.

Embodiments relate to the design of a device capable of increasing the electrical performance of an interconnect feature by amplifying the current carrying capacity of an interconnect feature. The device comprises a first body comprising a first surface with at least one nanoporous conductive structure protruding from the first surface. The device further comprises a second body comprising a second surface with arrays of nanofibers extending from the second surface and penetrating into corresponding nanoporous conductive structures to form conductive pathways between the first body and the second body.

Embodiments relate to the design of a device capable of increasing the electrical performance of an interconnect feature by amplifying the current carrying capacity of an interconnect feature. The device comprises a first body comprising a first surface with at least one nanoporous conductive structure protruding from the first surface. The device further comprises a second body comprising a second surface with arrays of nanofibers extending from the second surface and penetrating into corresponding nanoporous conductive structures to form conductive pathways between the first body and the second body.