A solid-state imaging device to be provided includes a first semiconductor device including a semiconductor layer in which a photoelectric conversion unit that photoelectrically converts incident light and a penetrating via are provided, a first connecting portion and a second connecting portion on the surface side of the semiconductor layer on the side that receives the light, and a connecting wiring line that connects the first connecting portion, the second connecting portion, and the penetrating via. The solid-state imaging device further includes a second semiconductor device that is mounted on the first semiconductor device with the first connecting portion. The solid-state imaging device is connected to an external terminal by the second connecting portion.

A circuit board on which a first semiconductor device or a second semiconductor device which is different from the first semiconductor device is exclusively mounted, wherein the circuit board comprises a region in which a component configured to form a circuit for achieving a function incorporated in the first semiconductor device but not incorporated in the second semiconductor device is to be mounted, and wherein the component is prevented from being mounted in the region in a case where the first semiconductor device is mounted, and the component is mounted in the region in a case where the second semiconductor device is mounted.

Provided herein is a method for producing hollow contact areas for insertion bonding, formed on a semiconductor substrate comprising a stack of one or more metallization layers on a surface of the substrate. Openings are etched in a dielectric layer by plasma etching, using a resist layer as a mask. The resist layer and plasma etch parameters are chosen to obtain openings with sloped sidewalls having a pre-defined slope, due to controlled formation of a polymer layer forming on the sidewalls of the resist hole and the hollow contact opening formed during etching. According to a preferred embodiment, metal deposited in the hollow contact areas and on top of the dielectric layer is planarized using chemical mechanical polishing, leading to mutually isolated contact areas. The disclosure is also related to components obtainable by the method and to a semiconductor package comprising such components.

Provided is a die stack structure including a first die, a second die, a first bonding structure, and a second bonding structure. The first bonding structure is disposed on a back side of the first die. The second bonding structure is disposed on a front side of the second die. The first die and the second die are bonded together via the first bonding structure and the second bonding structure and a bondable topography variation of a surface of the first bonding structure bonding with the second bonding structure is less than less than 1 m per 1 mm range. A method of manufacturing the die stack structure is also provided.

An upper redistribution wiring layer of a semiconductor package includes a protective layer provided on at least one upper insulating layer and having an opening that exposes at least a portion of an uppermost redistribution wiring among second redistribution wirings, and a bonding pad provided on the uppermost redistribution wiring through the opening. The bonding pad includes a first plating pattern formed on the uppermost redistribution wiring, the first plating pattern including a via pattern provided in the opening and a pad pattern formed on the via pattern to be exposed from the opening, a second plating pattern on the second plating pattern, and a third plating pattern on the second plating pattern.

A through electrode and a multilayer wiring are provided on a semiconductor substrate, and a bottom layer connection wiring, a lower layer connection wiring, an upper layer connection wiring, and a top layer connection wiring are provided in the multilayer wiring. The through electrode is connected to the bottom layer connection wiring, and a via is arranged at a position other than a position immediately above the through electrode.

A through electrode and a multilayer wiring are provided on a semiconductor substrate, and a bottom layer connection wiring, a lower layer connection wiring, an upper layer connection wiring, and a top layer connection wiring are provided in the multilayer wiring. The through electrode is connected to the bottom layer connection wiring, and a via is arranged at a position other than a position immediately above the through electrode.

A method for producing a stack of semiconductor devices and the stacked device obtained thereof are disclosed. In one aspect, the method includes providing a first semiconductor device comprising a dielectric layer with a hole, the hole lined with a metal layer and partially filled with solder material. The method also includes providing a second semiconductor device with a compliant layer having a metal protrusion through the compliant layer, the protrusion capped with a capping layer. The method further includes mounting the devices by landing the metal protrusion in the hole, where the compliant layer is spaced from the dielectric layer. The method includes thereafter reflowing the solder material, thereby bonding the devices such that the compliant layer is contacting the dielectric layer.

A package component includes a surface dielectric layer having a first planar surface, and a metal pad in the surface dielectric layer. The metal pad includes a diffusion barrier layer that includes sidewall portions, and a metallic material encircled by the sidewall portions of the diffusion barrier layer. The metallic material has a second planar surface level with the first planar surface. An air gap extends from the second planar surface of the metallic material into the metallic material. An edge of the air gap is aligned to an edge of the metallic material.

A package component includes a surface dielectric layer including a planar top surface, a metal pad in the surface dielectric layer and including a second planar top surface level with the planar top surface, and an air trench on a side of the metal pad. The sidewall of the metal pad is exposed to the air trench.