Connection pads are formed in interlayer films provided respectively in interconnection layers of a sensor substrate on which a sensor surface having pixels is formed and a signal processing substrate configured to perform signal processing on the sensor substrate to make an electrical connection between the sensor substrate and the signal processing substrate. Then, a metal oxide film is formed between the interlayer films of the sensor substrate and the signal processing substrate, between the connection pad formed on a side toward the sensor substrate and the interlayer film on a side toward the signal processing substrate, and between the connection pad formed on the side toward the signal processing substrate and the interlayer film on the side toward the sensor substrate. The present technology can be applied to a laminated-type CMOS image sensor, for example.

Representative implementations of techniques and devices are used to reduce or prevent conductive material diffusion into insulating or dielectric material of bonded substrates. Misaligned conductive structures can come into direct contact with a dielectric portion of the substrates due to overlap, especially while employing direct bonding techniques. A barrier interface that can inhibit the diffusion is disposed generally between the conductive material and the dielectric at the overlap.

Layer structures for making direct metal-to-metal bonds at low temperatures and shorter annealing durations in microelectronics are provided. Example bonding interface structures enable direct metal-to-metal bonding of interconnects at low annealing temperatures of 150° C. or below, and at a lower energy budget. The example structures provide a precise metal recess distance for conductive pads and vias being bonded that can be achieved in high volume manufacturing. The example structures provide a vertical stack of conductive layers under the bonding interface, with geometries and thermal expansion features designed to vertically expand the stack at lower temperatures over the precise recess distance to make the direct metal-to-metal bonds. Further enhancements, such as surface nanotexture and copper crystal plane selection, can further actuate the direct metal-to-metal bonding at lowered annealing temperatures and shorter annealing durations.

Layer structures for making direct metal-to-metal bonds at low temperatures and shorter annealing durations in microelectronics are provided. Example bonding interface structures enable direct metal-to-metal bonding of interconnects at low annealing temperatures of 150° C. or below, and at a lower energy budget. The example structures provide a precise metal recess distance for conductive pads and vias being bonded that can be achieved in high volume manufacturing. The example structures provide a vertical stack of conductive layers under the bonding interface, with geometries and thermal expansion features designed to vertically expand the stack at lower temperatures over the precise recess distance to make the direct metal-to-metal bonds. Further enhancements, such as surface nanotexture and copper crystal plane selection, can further actuate the direct metal-to-metal bonding at lowered annealing temperatures and shorter annealing durations.

According to one embodiment, a semiconductor device includes a first chip with a first electrode and a second electrode and a second chip with a third electrode and a fourth electrode. The first and second chips are bonded to each other with the first electrode contacting the third electrode and the second electrode contacting the fourth electrode. A thickness of the first electrode in a first direction perpendicular to a bonding interface between the first chip and the second chip is less than a thickness of the second electrode in the first direction. A planar area of the first electrode at the bonding interface is greater than a planar area of the second electrode at the bonding interface.

According to an embodiment, a semiconductor device includes a first chip including a substrate, and a second chip bonded to the first chip at a first surface. Each of the first chip and the second chip includes an element region, and an end region including a chip end portion. The first chip includes a plurality of first electrodes that are arranged on the first surface in the end region and are in an electrically uncoupled state. The second chip includes a plurality of second electrodes that are arranged on the first surface in the end region, are in an electrically uncoupled state, and are respectively in contact with the first electrodes.

Embodiments of a microelectronic assembly comprise a first integrated circuit (IC) die having first bond-pads on a first surface; an organic dielectric material in contact with the first surface; second bond-pads on a second surface of the organic dielectric material opposite to the first surface; through-dielectric vias (TDVs) in the dielectric material between the first bond-pads and the second bond-pads, wherein the TDVs are in direct contact with the first bond-pads and the second bond-pads; a second IC die embedded in the organic dielectric material and coupled to the first bond-pads by first interconnects; and a package substrate coupled to the second bond-pads by second interconnects.

The present disclosure relates to a semiconductor device, a manufacturing method, a solid state image sensor, and electronic equipment that can achieve further improvement in reliability. Connection pads are formed in interlayer films provided respectively in interconnection layers of a sensor substrate on which a sensor surface having pixels is formed and a signal processing substrate configured to perform signal processing on the sensor substrate to make an electrical connection between the sensor substrate and the signal processing substrate. Then, a metal oxide film is formed between the interlayer films of the sensor substrate and the signal processing substrate, between the connection pad formed on a side toward the sensor substrate and the interlayer film on a side toward the signal processing substrate, and between the connection pad formed on the side toward the signal processing substrate and the interlayer film on the side toward the sensor substrate. The present technology can be applied to a laminated-type CMOS image sensor, for example.

Embodiments are provided for package semiconductor devices, each device including: a low stress pad structure comprising: a dielectric layer, a seed layer having: a center section, and a ring section formed around the center section and over a top surface of the dielectric layer, wherein the ring section of the seed layer includes a set of elongated openings through which a portion of the top surface of the dielectric layer is exposed, and a metal layer having: an inner section formed over a top surface of the center section of the seed layer, and an outer section formed over a top surface of the ring section of the seed layer, wherein a bottom surface of the outer section of the metal layer directly contacts the portion of the top surface of the dielectric layer exposed through the set of elongated openings.

A light emitting package is provided, the light emitting package includes a carrier having a main part that has multiple chip bonding regions, and each the chip bonding regions has two neighboring conductive parts. An insulating part is disposed on the main part and portion of the two neighboring conductive parts, and multiple hollow-out structures are formed by the insulating part and corresponded in position to the chip bonding regions. Each of the hollow-out structures has a side wall that surrounds the chip bonding regions, and the portion of the tops of the two neighboring conductive parts are exposed from a bottom portion of the hollow-out structure, and multiple light emitting chips are disposed onto the chip bonding surfaces.