A semiconductor package includes a package substrate including a redistribution layer including first pads and second pads on an upper surface thereof and a solder mask layer having an opening exposing the first pads entirely and exposing at least portion of each of the second pads, a semiconductor chip on the upper surface of the package substrate and including connection pads electrically connected to the redistribution layer, connection bumps below the semiconductor chip and connecting the connection pads to the first pads, and a non-conductive film layer between the semiconductor chip and the package substrate, wherein the second pads are respectively disposed on both sides of the first pads at least in a first direction, and the connection bumps are spaced apart from the second pads and the solder mask layer in the first direction.

An integrated circuit (IC) package includes an interconnect comprising patches of unoxidized metal that are circumscribed by a region of roughened metal formed of oxidized metal. The IC package also includes a die mounted on the interconnect. The die is conductively coupled to at least a subset of the patches of unoxidized metal.