A method of manufacturing a semiconductor memory device includes processing a first substrate including a first align mark and a first structure, processing a second substrate including a second align mark and a second structure, orientating the first substrate and the second substrate such that the first structure and the second structure face each other, and controlling alignment between the first structure and the second structure by using the first align mark and the second align mark to couple the first structure with the second structure.

A semiconductor assembly packaging method, a semiconductor assembly and an electronic device are provided. The method comprises providing an interconnect board and at least one semiconductor device; aligning and attaching the at least one semiconductor device to the interconnect board by forming a plurality of alignment solder joints; applying pressure to the at least one semiconductor device and/or the interconnect board while the alignment solder joints are in a molten or partially molten state, whereby first connection terminals on the interconnect board are joined with and bonded to corresponding second connection terminals on the at least one semiconductor device. Using the packaging method, the semiconductor device and the interconnect board can be aligned accurately using relatively simple and low cost processes and equipment. The method can also be used to align and bond at least one semiconductor device to another semiconductor device.

A method of manufacturing a semiconductor memory device includes processing a first substrate including a first align mark and a first structure, processing a second substrate including a second align mark and a second structure, orientating the first substrate and the second substrate such that the first structure and the second structure face each other, and controlling alignment between the first structure and the second structure by using the first align mark and the second align mark to couple the first structure with the second structure.

A bonding tool for bonding a semiconductor element to a substrate on a bonding machine is provided. The bonding tool includes a body portion including a contact region for contacting the semiconductor element during a bonding process on the bonding machine. The bonding tool also includes a standoff extending from the body portion, and configured to contact the substrate during at least a portion of the bonding process.

Packaging methods for semiconductor devices and methods of packaging thereof are disclosed. In some embodiments, a device includes a packaging apparatus and contact pads disposed on the packaging apparatus. The contact pads are arranged in an array of rows and columns. The contact pads include first contact pads proximate a perimeter region of the packaging apparatus and second contact pads disposed in an interior region of the packaging apparatus. A dam structure that is continuous is disposed around the second contact pads. The contact pads comprise a mounting region for a semiconductor device.

A circuit backplane of a display panel, a method for manufacturing the same, and a display panel are provided. The circuit backplane includes a substrate and a plurality of circuit regions on the substrate. Each of the plurality of circuit regions includes a cathode soldered electrode, an anode soldered electrode, and a flow blocking island that are on the substrate. The flow blocking island is between the cathode soldered electrode and the anode soldered electrode, and in a thickness direction of the circuit backplane, a height of the flow blocking island is greater than each of a height of the cathode soldered electrode and a height of the anode soldered electrode.

A semiconductor device includes a semiconductor element, an internal electrode connected to the semiconductor element, a sealing resin covering the semiconductor element and a portion of the internal electrode, and an external electrode exposed from the sealing resin and connected to the internal electrode. The internal electrode includes a wiring layer and a columnar portion, where the wiring layer has a wiring layer front surface facing the back surface of the semiconductor element and a wiring layer back surface facing opposite from the wiring layer front surface in the thickness direction. The columnar portion protrudes in the thickness direction from the wiring layer front surface. The columnar portion has an exposed side surface facing in a direction perpendicular to the thickness direction. The external electrode includes a first cover portion covering the exposed side surface.

A semiconductor device comprising: substrate having main surface facing thickness direction; wirings arranged on main surface; semiconductor element having back surface facing the main surface and electrodes formed on back surface, wherein the electrodes are bonded to the wirings; and columnar wirings located outside the semiconductor element as viewed along the thickness direction, protrude in direction away from the main surface in the thickness direction, and are arranged on the wirings, wherein the semiconductor element includes first circuit and second circuit, wherein the electrodes include first electrodes electrically connected to the first circuit and second electrodes electrically connected to the second circuit, wherein the columnar wirings include first columnar portions electrically connected to the first electrodes and second columnar portions electrically connected to the second electrodes, and wherein area of each first columnar portions is larger than area of each second columnar portions in the thickness direction.

A circuit substrate that includes a substrate having a major surface, a multilayer body on the major surface, and an insulating layer that covers the major surface. The multilayer body includes a first layer and a second layer that overlies the first layer. The first layer is made of a first metal as a main material thereof, and the second layer is made of a second metal as a main material thereof. The second metal has a higher solder wettability than the first metal. As viewed perpendicular to the major surface, the insulating layer is spaced from and surrounds the surface of the second layer so as to define a recess between the multilayer body and the insulating layer.

A technique for fabricating bumps on a substrate is disclosed. A substrate that includes a set of pads formed on a surface thereof is prepared. A bump base is formed on each pad of the substrate. Each bump base has a tip extending outwardly from the corresponding pad. A resist layer is patterned on the substrate to have a set of holes through the resist layer. Each hole is aligned with the corresponding pad and having space configured to surround the tip of the bump base formed on the corresponding pad. The set of the holes in the resist layer is filled with conductive material to form a set of bumps on the substrate. The resist layer is stripped from the substrate with leaving the set of the bumps.