A substrate (3) and two or more different chips (1a, 1b) having different heating properties (e.g. caused by different dimensions (surface area and/or thickness), heat capacity (C1, C2), absorptivity, conductivity, number and/or size of solder bonds) are provided. A solder material (2) is disposed between the chips (1a, 1b) and the substrate (3). A flash lamp (5) generates a light pulse (6) for heating the chips (1a, 1b), wherein the solder material (2) is at least partially melted by contact with the heated chips (1a, 1b). A masking device (7) is disposed between the flash lamp (5) and the chips (1a, 1b) causing different light intensities (1a, 1b) in different areas (6a, 6b) of the light pulse (6) passing the masking device (7), thereby heating the chips (1a, 1b) with different light intensities (1a, 1b). This may compensate the different heating properties to reduce a spread in temperature between the chips (1a, 1b) as a result of the heating by the light pulse (6). The chips (1a, 1b) may be releasably carried by a chip carrier disposed between the flash lamp (5) and the substrate (3) before being positioned on the substrate (3), wherein the light (6a, 6b) of the light pulse (6) transmitted by the masking device (7) is projected onto the chips (1a, 1b) held by the chip carrier for heating the chips (1a, 1b), releasing them from the chip carrier and transferring them to the substrate (3), wherein the heated chips (1a, 1b) cause melting of the solder material (2) between the chips (1a, 1b) and the substrate (3) for attaching the chips (1a, 1b) to the substrate (3).

To miniaturize metal columns. A semiconductor device includes a metal column (14) that extends in a stretching direction; a polymer layer (16) that surrounds the metal column from a direction crossing the stretching direction; and a guide (12) that surrounds the polymer layer in the crossing direction so as to be spaced from the metal column with the polymer layer interposed therebetween. A method for manufacturing semiconductor devices includes a step of filling a mixture (20) containing metal particles (22) and polymers (24) in a guide (12); and a step of subjecting the mixture to a heat treatment so that the polymers agglomerate to the guide to form a polymer layer (16) that makes contact with the guide and the metal particles agglomerate away from the guide with the polymer layer interposed therebetween to form a metal column (14) that stretches in a stretching direction of the guide from the metal particles.

A method of forming a coaxial wire that includes providing a sacrificial trace structure using an additive forming method, the sacrificial trace structure having a geometry for the coaxial wire, and forming a continuous seed metal layer on the sacrificial trace structure.

The sacrificial trace structure may be removed and a first interconnect metal layer may be formed on the continuous seed layer. An electrically insulative layer may then be formed on the first interconnect metal layer, and a second interconnect metal layer is formed on the electrically insulative layer. Thereafter, a dielectric material is formed on the second interconnect metal layer to encapsulate a majority of an assembly of the first interconnect metal layer, electrically insulative layer and second interconnect metal layer that provides said coaxial wire. Ends of the coaxial wire may be exposed through opposing surfaces of the dielectric material to provide that the coaxial wire extends through that dielectric material.

A method of forming a coaxial wire that includes providing a sacrificial trace structure using an additive forming method, the sacrificial trace structure having a geometry for the coaxial wire, and forming a continuous seed metal layer on the sacrificial trace structure.

The sacrificial trace structure may be removed and a first interconnect metal layer may be formed on the continuous seed layer. An electrically insulative layer may then be formed on the first interconnect metal layer, and a second interconnect metal layer is formed on the electrically insulative layer. Thereafter, a dielectric material is formed on the second interconnect metal layer to encapsulate a majority of an assembly of the first interconnect metal layer, electrically insulative layer and second interconnect metal layer that provides said coaxial wire. Ends of the coaxial wire may be exposed through opposing surfaces of the dielectric material to provide that the coaxial wire extends through that dielectric material.

Methods, systems, and structures relating to flip-chip bonding are described. A processor can determine a plurality of target solder volumes to be deposited on a plurality of pads on a surface of a substrate. The plurality of target solder volumes can be variable among the plurality of pads. The processor can determine different thicknesses of different portions of a layer of resist to be deposited across the surface of the substrate. The different thicknesses can define a plurality of solder resist openings having sizes that comply with the plurality of target solder volumes.

A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and a method of manufacturing thereof, that comprises a first semiconductor die, a plurality of adhesive regions spaced apart from each other on the first semiconductor die, and a second semiconductor die adhered to the plurality of adhesive regions.

A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and a method of manufacturing thereof, that comprises a first semiconductor die, a plurality of adhesive regions spaced apart from each other on the first semiconductor die, and a second semiconductor die adhered to the plurality of adhesive regions.

A method of forming a coaxial wire that includes providing a sacrificial trace structure using an additive forming method, the sacrificial trace structure having a geometry for the coaxial wire, and forming a continuous seed metal layer on the sacrificial trace structure. The sacrificial trace structure may be removed and a first interconnect metal layer may be formed on the continuous seed layer. An electrically insulative layer may then be formed on the first interconnect metal layer, and a second interconnect metal layer is formed on the electrically insulative layer. Thereafter, a dielectric material is formed on the second interconnect metal layer to encapsulate a majority of an assembly of the first interconnect metal layer, electrically insulative layer and second interconnect metal layer that provides said coaxial wire. Ends of the coaxial wire may be exposed through opposing surfaces of the dielectric material to provide that the coaxial wire extends through that dielectric material.

A method of forming a coaxial wire that includes providing a sacrificial trace structure using an additive forming method, the sacrificial trace structure having a geometry for the coaxial wire, and forming a continuous seed metal layer on the sacrificial trace structure. The sacrificial trace structure may be removed and a first interconnect metal layer may be formed on the continuous seed layer. An electrically insulative layer may then be formed on the first interconnect metal layer, and a second interconnect metal layer is formed on the electrically insulative layer. Thereafter, a dielectric material is formed on the second interconnect metal layer to encapsulate a majority of an assembly of the first interconnect metal layer, electrically insulative layer and second interconnect metal layer that provides said coaxial wire. Ends of the coaxial wire may be exposed through opposing surfaces of the dielectric material to provide that the coaxial wire extends through that dielectric material.

Highly reliable chip mounting is accomplished by using a substrate having such a shape that a stress exerted on a flip-chip-connected chip can be reduced, so that the stress exerted on the chip is reduced and separation of an interlayer insulating layer having a low dielectric constant (low-k) is minimized. Specifically, in a chip mounting structure, a chip including an interlayer insulating layer having a low dielectric constant (low-k) is flip-chip connected to a substrate via bumps is shown. In the chip mounting structure, the substrate has such a shape that a mechanical stress exerted on the interlayer insulating layer at corner portions of the chip due to a thermal stress is reduced, the thermal stress occurring due to a difference in coefficient of thermal expansion between the chip and the substrate.