A method for manufacturing metal powder comprising: providing a basic metal salt solution; contacting the basic metal salt solution with a reducing agent to precipitate metal powder therefrom; and recovering precipitated metal powder from the solvent.

A method for manufacturing metal powder comprising: providing a basic metal salt solution; contacting the basic metal salt solution with a reducing agent to precipitate metal powder therefrom; and recovering precipitated metal powder from the solvent.

A semiconductor structure and methods of forming the semiconductor structure include a solder bump self-aligned to a through-substrate-via, wherein the solder bump and the through-substrate-via are formed of a conductive metal material, and wherein the through-substrate-via is coupled to a buried metallization layer, which is formed of a different conductive metal material.

A semiconductor structure and methods of forming the semiconductor structure include a solder bump self-aligned to a through-substrate-via, wherein the solder bump and the through-substrate-via are formed of a conductive metal material, and wherein the through-substrate-via is coupled to a buried metallization layer, which is formed of a different conductive metal material.

Apparatus and method associated with surface structures of compute component packages are disclosed herein. In embodiments, an apparatus may include a plurality of structures provided on a surface of a compute component package, wherein the plurality of structures are to be used to attach and electrically couple the compute component package to another device, and wherein a structure of the plurality of structures includes first and second portions, the second portion disposed further from the surface than the first portion, and the first portion to comprise a material different from the second portion.

A method of forming a coaxial wire that includes providing a sacrificial trace structure using an additive forming method, the sacrificial trace structure having a geometry for the coaxial wire, and forming a continuous seed metal layer on the sacrificial trace structure. The sacrificial trace structure may be removed and a first interconnect metal layer may be formed on the continuous seed layer. An electrically insulative layer may then be formed on the first interconnect metal layer, and a second interconnect metal layer is formed on the electrically insulative layer. Thereafter, a dielectric material is formed on the second interconnect metal layer to encapsulate a majority of an assembly of the first interconnect metal layer, electrically insulative layer and second interconnect metal layer that provides said coaxial wire. Ends of the coaxial wire may be exposed through opposing surfaces of the dielectric material to provide that the coaxial wire extends through that dielectric material.

A method of forming a coaxial wire that includes providing a sacrificial trace structure using an additive forming method, the sacrificial trace structure having a geometry for the coaxial wire, and forming a continuous seed metal layer on the sacrificial trace structure. The sacrificial trace structure may be removed and a first interconnect metal layer may be formed on the continuous seed layer. An electrically insulative layer may then be formed on the first interconnect metal layer, and a second interconnect metal layer is formed on the electrically insulative layer. Thereafter, a dielectric material is formed on the second interconnect metal layer to encapsulate a majority of an assembly of the first interconnect metal layer, electrically insulative layer and second interconnect metal layer that provides said coaxial wire. Ends of the coaxial wire may be exposed through opposing surfaces of the dielectric material to provide that the coaxial wire extends through that dielectric material.

Systems and techniques that facilitate uniform qubit chip gaps via injection-molded solder pillars are provided. In various embodiments, a device can comprise one or more injection-molded solder interconnects. In various aspects, the one or more injection-molded solder interconnects can couple at least one qubit chip to an interposer chip. In various embodiments, the device can further comprise one or more injection-molded solder pillars. In various instances, the one or more injection-molded solder pillars can be between the at least one quit chip and the interposer chip. In various cases, the one or more injection-molded solder pillars can be in parallel with the one or more injection-molded solder interconnects. In various embodiments, the one or more injection-molded solder pillars can facilitate and/or maintain a uniform gap between the at least one qubit chip and the interposer chip. In various embodiments, a melting point of the one or more injection-molded solder pillars can be higher than a melting point of the one or more injection-molded solder interconnects. In various embodiments, the one or more injection-molded solder pillars can be superconductors. In various embodiments, a yield strength of the one or more injection-molded solder pillars can be between 3,000 pounds per square inch and 15,000 pounds per square inch, which can be higher than a yield strength of the one or more injection-molded solder interconnects. In various embodiments, the one or more injection-molded solder pillars can be binary tin alloys, tertiary tin alloys, and/or quaternary tin alloys.

A SnAgCuSbBi-based Pb-free solder alloy is disclosed. The disclosed solder alloy is particularly suitable for, but not limited to, producing solder joints, in the form of solder preforms, solder balls, solder powder, or solder paste (a mixture of solder powder and flux), for harsh environment electronics.

The present disclosure provides a method for preparing a semiconductor package having a standard size from a die having a size smaller than the standard size. The method includes: providing a wafer; forming a die on the wafer, wherein the die has a size smaller than one-half of a standard size 0201; dicing the die from the wafer; encapsulating the die to form an encapsulated die; and singulating the encapsulated die to form a semiconductor package having a size equal to or larger than the standard size 0201.