An integrated circuit and a method for designing an IC wherein the base or host chip is bonded to smaller chiplets via DBI technology. The bonding of chip to chiplet creates an uneven or multi-level surface of the overall chip requiring a releveling for future bonding. The uneven surface is built up with plating of bumps and subsequently releveled with various methods including planarization.

A semiconductor device includes a conductive pattern disposed over a semiconductor substrate, and an interconnect structure disposed over the conductive pattern. The semiconductor device also includes an interconnect liner formed between the interconnect structure and the conductive pattern and surrounding the interconnect structure. The inner sidewall surfaces of the interconnect liner are in direct contact with the interconnect structure, and a maximum distance between outer sidewall surfaces of the interconnect liner is greater than a width of the conductive pattern. The semiconductor device further includes a semiconductor die bonded to the semiconductor substrate. The semiconductor die includes a conductive pad facing the interconnect structure, wherein the conductive pad is electrically connected to the conductive pattern.

A package that includes a substrate, an integrated device coupled to the substrate, and a capacitor structure located between the substrate and the integrated device. The capacitor structure includes a capacitor substrate comprising a first trench, a first electrically conductive layer located in the first trench, a dielectric layer located over the first electrically conductive layer, and a second electrically conductive layer located over the dielectric layer. The first electrically conductive layer over the first trench, the dielectric layer and the second electrically conductive layer are configured as a first capacitor.

Disclosed is a microelectronic device assembly comprising a substrate having conductors exposed on a surface thereof. Two or more stacks of microelectronic devices are located on the substrate, and microelectronic devices of the stacks are connected to vertical conductive paths external to the stacks and extending to the substrate and to lateral conductive paths extending between the stacks. Methods of fabrication are also disclosed.

Disclosed is a microelectronic device assembly comprising a substrate having conductors exposed on a surface thereof. Two or more microelectronic devices are stacked on the substrate, each microelectronic device comprising an active surface operably coupled to conductive traces extending over a dielectric material to via locations beyond at least one side of the stack, at least one surface mount component operably coupled to conductive traces of at least one dielectric material, and vias extending through the dielectric materials at the via locations and comprising conductive material in contact with at least some of the conductive traces of each of the two or more electronic devices and extending to exposed conductors of the substrate.

Disclosed is a microelectronic device assembly comprising a substrate having conductors exposed on a surface thereof. Two or more microelectronic devices are stacked on the substrate, each microelectronic device comprising an active surface having bond pads operably coupled to conductive traces extending over a dielectric material to via locations beyond at least one side of the stack, and vias extending through the dielectric materials at the via locations and comprising conductive material in contact with at least some of the conductive traces of each of the two or more electronic devices and extending to exposed conductors of the substrate. Methods of fabrication and related electronic systems are also disclosed.

Disclosed is a microelectronic device assembly comprising a substrate having conductors exposed on a surface thereof. Two or more microelectronic devices are stacked on the substrate and the components are connected with conductive material in preformed holes in dielectric material in the bond lines aligned with TSVs of the devices and the exposed conductors of the substrate. Methods of fabrication are also disclosed.

A micro LED display manufacturing method according to various embodiments may include: a first operation of bonding an anisotropic conductive film including a plurality of conductive particles onto one surface of a prepared substrate, the one surface including a circuit part; a second operation of forming a bonding layer on the anisotropic conductive film; a third operation of positioning a plurality of micro LED chips above the bonding layer, the micro LED chips being arranged on a carrier substrate while being spaced a first distance apart from the substrate; a fourth operation of attaching the plurality of micro LED chips onto the bonding layer by means of laser transfer; and a fifth operation of forming a conductive structure for electrically connecting a connection pad to the circuit part through the conductive particles by means of heating and pressurizing.

A semiconductor structure including a first semiconductor die, a second semiconductor die, a passivation layer, an anti-arcing pattern, and conductive terminals is provided. The second semiconductor die is stacked over the first semiconductor die. The passivation layer covers the second semiconductor die and includes first openings for revealing pads of the second semiconductor die. The anti-arcing pattern is disposed over the passivation layer. The conductive terminals are disposed over and electrically connected to the pads of the second semiconductor die.

An integrated circuit and a method for designing an IC wherein the base or host chip is bonded to smaller chiplets via DBI technology. The bonding of chip to chiplet creates an uneven or multi-level surface of the overall chip requiring a releveling for future bonding. The uneven surface is built up with plating of bumps and subsequently releveled with various methods including planarization.