A photosensitive resin composition comprising (A) a silphenylene and polyether structurecontaining polymer and (B) a photoacid generator is coated onto a substrate to form a photosensitive resin coating which has improved substrate adhesion, a pattern forming ability, crack resistance, and reliability as protective film.

A method for fabricating bump structures on chips with a panel type process is provided. First, a panel type substrate is provided. Semiconductor chips are fixed on the panel type substrate. Each semiconductor chip includes metal pads and a passivation layer exposing the metal pads. At least an electroless plating process is performed to form under bump metallurgy structures on the metal pads. The method simplifies the processes of forming electrical connections for semiconductor chips. The panel type process can effectively increase the yield, and reduce the manufacturing cost.

The present invention provides a method for preparing a dielectric layer on a surface of a wafer, a wafer structure, and a method for shaping a bump. The preparation method includes: providing a wafer; forming an alignment mark on the wafer, the thickness of the alignment mark being not less than 0.3 ?m; and forming a dielectric layer on the wafer where the alignment mark is formed. In the present application, before the dielectric layer is shaped on a surface of the wafer, the alignment mark is prepared in advance on the surface of the wafer, thereby avoiding the need of reworking due to an invisible alignment mark in a preparation stage of the dielectric layer, and ensuring the continuity of the process.

A semiconductor device including: a first formation site and a second formation site for forming a first conductive bump and a second conductive bump; when a first environmental density corresponding to the first formation site is greater than a second environmental density corresponding to the second formation site, a cross sectional area of the second formation site is greater than a cross sectional area of the first formation site; wherein the first environmental density is determined by a number of formation sites around the first formation site in a predetermined range and the second environmental density is determined by a number of formation sites around the second formation site in the predetermined range; wherein a first area having the first environmental density forms an ellipse layout while a second area having the second environmental density forms a strip layout surrounding the ellipse layout.

A technique for fabricating bumps on a substrate is disclosed. A substrate that includes a set of pads formed on a surface thereof is prepared. A bump base is formed on each pad of the substrate. Each bump base has a tip extending outwardly from the corresponding pad. A resist layer is patterned on the substrate to have a set of holes through the resist layer. Each hole is aligned with the corresponding pad and having space configured to surround the tip of the bump base formed on the corresponding pad. The set of the holes in the resist layer is filled with conductive material to form a set of bumps on the substrate. The resist layer is stripped from the substrate with leaving the set of the bumps.

Embodiments of the invention are directed to a method and resulting structures for forming optically readable chip identification (CID) codes using dummy controlled collapse chip connection (C4) bumps. In a non-limiting embodiment of the invention, a product chip is formed on a wafer. A chip location identifier including a plurality of controlled collapse chip connection (C4) bumps is formed on a surface of the product chip. The chip location identifier encodes a unique location of the product chip on the wafer prior to dicing. The plurality of C4 bumps are arranged into one or more optically readable alphanumeric characters.

A method for fabricating bump structures on chips with a panel type process is provided. First, a panel type substrate is provided. Semiconductor chips are fixed on the panel type substrate. Each semiconductor chip includes metal pads and a passivation layer exposing the metal pads. At least an electroless plating process is performed to form under bump metallurgy structures on the metal pads. The method simplifies the processes of forming electrical connections for semiconductor chips. The panel type process can effectively increase the yield, and reduce the manufacturing cost.

Highly reliable chip mounting is accomplished by using a substrate having such a shape that a stress exerted on a flip-chip-connected chip can be reduced, so that the stress exerted on the chip is reduced and separation of an interlayer insulating layer having a low dielectric constant (low-k) is minimized. Specifically, in a chip mounting structure, a chip including an interlayer insulating layer having a low dielectric constant (low-k) is flip-chip connected to a substrate via bumps is shown. In the chip mounting structure, the substrate has such a shape that a mechanical stress exerted on the interlayer insulating layer at corner portions of the chip due to a thermal stress is reduced, the thermal stress occurring due to a difference in coefficient of thermal expansion between the chip and the substrate.

The present invention discloses a connection component, connector, manufacturing method for the same and panel component. The connection component includes a first connector and a second connector electrically connected to the first connector, wherein, between the first connector and the second connector, a connection adhesive is provided, the first connector and/or the second connector both include a base body and multiple connection terminals, wherein the multiple connection terminals are disposed on the base body, a terminal portion of each connection terminal has a protrusion, the protrusion has a saw-tooth shape, and the saw-tooth shape has a regular pattern or a non-regular pattern, Accordingly, the present invention can enhance the reliability of the connection and increase the production yield.

An electronic device includes a semiconductor die having a first side, an orthogonal second side for mounting to a substrate or circuit board, a conductive terminal on the first side, the conductive terminal having a center that is spaced apart from the second side by a first distance along a direction, and a solder structure extending on the conductive terminal, the solder structure having a center that is spaced apart from the center of the conductive terminal by a non-zero second distance along the direction.