Embodiments herein relate to systems, apparatuses, or processes directed to an interconnect joint that includes multiple core balls within a solder compound where the multiple core balls are substantially linearly aligned. The multiple core balls, which may include copper or be a polymer, couple with each other within the solder and form a substantially linear alignment during reflow. In embodiments, four or more core balls may be used to achieve a high aspect ratio interconnect joint with a tight pitch.

A technique for fabricating bumps on a substrate is disclosed. A substrate that includes a set of pads formed on a surface thereof is prepared. A bump base is formed on each pad of the substrate. Each bump base has a tip extending outwardly from the corresponding pad. A resist layer is patterned on the substrate to have a set of holes through the resist layer. Each hole is aligned with the corresponding pad and having space configured to surround the tip of the bump base formed on the corresponding pad. The set of the holes in the resist layer is filled with conductive material to form a set of bumps on the substrate. The resist layer is stripped from the substrate with leaving the set of the bumps.

A technique for fabricating bumps on a substrate is disclosed. A substrate that includes a set of pads formed on a surface thereof is prepared. A bump base is formed on each pad of the substrate. Each bump base has a tip extending outwardly from the corresponding pad. A resist layer is patterned on the substrate to have a set of holes through the resist layer. Each hole is aligned with the corresponding pad and having space configured to surround the tip of the bump base formed on the corresponding pad. The set of the holes in the resist layer is filled with conductive material to form a set of bumps on the substrate. The resist layer is stripped from the substrate with leaving the set of the bumps.

A semiconductor manufacturing apparatus includes; a component separating apparatus configured to separate a defective component from a substrate, a bump conditioning apparatus including an end mill cutter and receiving the substrate following separation of the defective component from the substrate, the bump conditioning apparatus being configured to cut a first connection bump using the end mill cutter to provide a conditioned first connection bump, and the first connection bump being exposed by separating the defective component from the substrate, and a component attaching apparatus configured to receive the substrate following provision of the conditioned first connection bump, and mount a new component including a second connection bump to the substrate by coupling the second connection bump and the conditioned first connection bump.

A method includes picking up a first package component, removing an oxide layer on an electrical connector of the first package component, placing the first package component on a second package component after the oxide layer is removed, and bonding the first package component to the second package component.

A microelectronic device has a pillar connected to an external terminal by an intermetallic joint. Either the pillar or the external terminal, or both, include copper in direct contact with the intermetallic joint. The intermetallic joint includes at least 90 weight percent of at least one copper-tin intermetallic compound. The intermetallic joint is free of voids having a combined volume greater than 10 percent of a volume of the intermetallic joint; and free of a void having a volume greater than 5 percent of the volume of the intermetallic joint. The microelectronic device may be formed using solder which includes at least 93 weight percent tin, 0.5 weight percent to 5.0 weight percent silver, and 0.4 weight percent to 1.0 weight percent copper, to form a solder joint between the pillar and the external terminal, followed by thermal aging to convert the solder joint to the intermetallic joint.

Embodiments of the inventive concepts provide a method of manufacturing a semiconductor device and a cleaning composition for an adhesive layer. The method includes preparing a semiconductor substrate to which an adhesive layer adheres, removing the adhesive layer from the semiconductor substrate, and applying a cleaning composition to the semiconductor substrate to remove a residue of the adhesive layer. The cleaning composition includes a solvent including a ketone compound and having a content that is equal to or greater than 40 wt % and less thaadminn 90 wt %, quaternary ammonium salt, and primary amine.

Systems and methods are provided for method for etch assisted gold (Au) through silicon mask plating (EAG-TSM). An example method comprises providing a seed layer on a substrate and providing a silicon mask on at least a portion of the seed layer on the substrate. The silicon mask includes one or more via to be filled with Au. The masked substrate is subjected to at least one processing cycle, each processing cycle including an Au plating sub-step and an etch treatment sub-step. The cycles are repeated until a selected via fill thickness is achieved.

Systems and methods are provided for method for etch assisted gold (Au) through silicon mask plating (EAG-TSM). An example method comprises providing a seed layer on a substrate and providing a silicon mask on at least a portion of the seed layer on the substrate. The silicon mask includes one or more via to be filled with Au. The masked substrate is subjected to at least one processing cycle, each processing cycle including an Au plating sub-step and an etch treatment sub-step. The cycles are repeated until a selected via fill thickness is achieved.

A method for printing solder onto a wafer (101) including the steps of depositing solder paste (102) onto a wafer (101), applying an inline reflow process to the deposited solder paste (102) to form solder bumps (103) on the wafer (101), and cleaning the reflowed solder bumps (103). The method for printing solder onto the wafer (101) is based on a system thereof that includes a wafer solder printer (1), an inline reflow means (2) and a de-fluxing means (3), wherein each step has its parameters optimized by means of a staging process control.