H01L2224/1182

Chiplets with connection posts

A component includes a plurality of electrical connections on a process side opposed to a back side of the component. Each electrical connection includes an electrically conductive multi-layer connection post protruding from the process side. A printed structure includes a destination substrate and one or more components. The destination substrate has two or more electrical contacts and each connection post is in contact with, extends into, or extends through an electrical contact of the destination substrate to electrically connect the electrical contacts to the connection posts. The connection posts or electrical contacts are deformed. Two or more connection posts can be electrically connected to a common electrical contact.

Devices with three-dimensional structures and support elements to increase adhesion to substrates

Methods of forming supports for 3D structures on semiconductor structures comprise forming the supports from photodefinable materials by deposition, selective exposure and curing. Semiconductor dice including 3D structures having associated supports, and semiconductor devices are also disclosed.

Package with conductive underfill ground plane

Embodiments for a packaged semiconductor device and methods of making are provided herein, which includes a packaged semiconductor device including: a semiconductor die; a carrier; a plurality of electrical connections formed between the semiconductor die and the carrier; an electrical isolation layer that covers an outer surface of each of the plurality of electrical connections; and a conductive underfill structure between the semiconductor die and the carrier, and surrounding each of the plurality of electrical connections, wherein the electrical isolation layer electrically isolates each electrical connection from the conductive underfill structure.

Package with conductive underfill ground plane

Embodiments for a packaged semiconductor device and methods of making are provided herein, which includes a packaged semiconductor device including: a semiconductor die; a carrier; a plurality of electrical connections formed between the semiconductor die and the carrier; an electrical isolation layer that covers an outer surface of each of the plurality of electrical connections; and a conductive underfill structure between the semiconductor die and the carrier, and surrounding each of the plurality of electrical connections, wherein the electrical isolation layer electrically isolates each electrical connection from the conductive underfill structure.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate and a metal holder. The substrate includes at least one bonding pad disposed adjacent to its surface and the metal holder is disposed adjacent to the bonding pad.

METHOD FOR CONNECTING CROSS-COMPONENTS AT OPTIMISED DENSITY
20210280628 · 2021-09-09 ·

A method for electrical connection by hybridisation of a first component with a second component. The method comprises the following steps: forming pads of ductile material in contact respectively with connection zones of the first component; forming inserts of conductive material in contact with the connection zones of the second component; forming hybridisation barriers arranged between the inserts and electrically insulated from each other, the first and second hybridisation barriers serving as a barrier by containing the deformation of the pads of ductile material during the connection of the connection zones of the first component with those of the second component. The disclosure also relates to an assembly of two connected components.

METHOD FOR CONNECTING CROSS-COMPONENTS AT OPTIMISED DENSITY
20210280628 · 2021-09-09 ·

A method for electrical connection by hybridisation of a first component with a second component. The method comprises the following steps: forming pads of ductile material in contact respectively with connection zones of the first component; forming inserts of conductive material in contact with the connection zones of the second component; forming hybridisation barriers arranged between the inserts and electrically insulated from each other, the first and second hybridisation barriers serving as a barrier by containing the deformation of the pads of ductile material during the connection of the connection zones of the first component with those of the second component. The disclosure also relates to an assembly of two connected components.

Microelectronic structures having multiple microelectronic devices connected with a microelectronic bridge embedded in a microelectronic substrate

A microelectronic structure includes a microelectronic substrate having a first surface and a cavity extending into the substrate from the microelectronic substrate first surface, a first microelectronic device and a second microelectronic device attached to the microelectronic substrate first surface, and a microelectronic bridge disposed within the microelectronic substrate cavity and attached to the first microelectronic device and to the second microelectronic device. In one embodiment, the microelectronic structure may include a reconstituted wafer formed from the first microelectronic device and the second microelectronic device. In another embodiment, a flux material may extend between the first microelectronic device and the microelectronic bridge and between the second microelectronic device and the microelectronic bridge.

Microelectronic structures having multiple microelectronic devices connected with a microelectronic bridge embedded in a microelectronic substrate

A microelectronic structure includes a microelectronic substrate having a first surface and a cavity extending into the substrate from the microelectronic substrate first surface, a first microelectronic device and a second microelectronic device attached to the microelectronic substrate first surface, and a microelectronic bridge disposed within the microelectronic substrate cavity and attached to the first microelectronic device and to the second microelectronic device. In one embodiment, the microelectronic structure may include a reconstituted wafer formed from the first microelectronic device and the second microelectronic device. In another embodiment, a flux material may extend between the first microelectronic device and the microelectronic bridge and between the second microelectronic device and the microelectronic bridge.

Semiconductor package with composite thermal interface material structure and method of forming the same

A semiconductor package is provided. The semiconductor package includes a substrate and a semiconductor die over the substrate. A heat-dissipating feature covers the substrate and the semiconductor die, and a composite thermal interface material (TIM) structure is thermally bonded between the semiconductor die and the heat-dissipating feature. The composite TIM structure includes a metal-containing matrix material layer and polymer particles embedded in the metal-containing matrix material layer.