A semiconductor device includes a first semiconductor chip including a conductive pad, an insulating layer provided on the conductive pad, and having an aperture exposing a part of the conductive pad, and a first bump layer provided on the insulating layer and connected to the conductive pad via the aperture, and a second semiconductor chip including an electrode and a second bump layer provided on the electrode. The first bump layer includes a recessed portion provided at the aperture and in contact with the second bump layer, and a raised portion provided adjacent the aperture and in contact with the second bump layer.

A method for fabricating a low resistance, low inductance device for high current semiconductor flip-chip products. A structure is produced, which comprises a semiconductor chip with metallization traces, copper lines in contact with the traces, and copper bumps located in an orderly and repetitive arrangement on each line so that the bumps of one line are positioned about midway between the corresponding bumps of the neighboring lines. A substrate is provided which has elongated copper leads with first and second surfaces, the leads oriented at right angles to the lines. The first surface of each lead is connected to the corresponding bumps of alternating lines using solder elements. Finally, the assembly is encapsulated in molding compound so that the second lead surfaces remain un-encapsulated.

In one instance, a semiconductor package includes a metal leadframe having a first plurality of openings extending partially into the leadframe from the first side and a second plurality of openings extending partially into the leadframe from the second side together forming a plurality of leads. A pre-mold compound is positioned in the second plurality of openings that at least partially supports the plurality of leads. The semiconductor package has a plurality of bumps extending from the landing sites to a semiconductor die and a molding compounding at least partially covering the plurality of bumps and the metal leadframe. Other packages and methods are disclosed.

A cryogenic under bump metallization (UBM) stack includes an adhesion and barrier layer and a conductive pillar on the adhesion and barrier layer. The conductive pillar functions as a solder wetting layer of the UBM stack and has a thickness. An indium superconducting solder bump is on the conductive pillar. The thickness of the conductive pillar is sufficient to prevent intermetallic regions, which form in the conductive pillar at room temperature due to interdiffusion, from extending through the entire thickness of the conductive pillar to maintain the structural integrity of the UBM stack. The indium (In) solder bump may be formed through electroplating, with the conductive pillar being copper (Cu) and the adhesion and barrier layer being titanium tungsten (TiW) and a thin seed layer of copper (Cu), or a layer of titanium (Ti).

A method of manufacturing a semiconductor structure includes forming a precursor structure including a plurality of conductive pads on a substrate, an etch stop layer between the conductive pads, and an UBM layer on the conductive pads and the etch stop layer. A plurality of mask structures are formed on the UBM layer, and a plurality of openings are formed between thereof. Each of the mask structures is located on one of the conductive pads, and the openings expose a first portion of the UBM layer. A supporting layer is formed in the openings. The mask structures are removed to form a plurality of cavities exposing a second portion of the UBM layer. A conductive material layer is formed in the cavities. The supporting layer is removed. The first portion of the UBM layer is removed to form a plurality of conductive bumps separated from each other.

The present disclosure provides a semiconductor package, including a substrate, an active region in the substrate, an interconnecting layer over the active region, a conductive pad over the interconnecting layer, surrounded by a dielectric layer. At least two discrete regions of the conductive pad are free from coverage of the dielectric layer. A method of manufacturing the semiconductor package is also disclosed.

Provided is a method of manufacturing compliant bumps, the method including preparing an electronic device including at least one conductive pad, forming an elastic resin layer on the electronic device, forming a photoresist layer on the elastic resin layer, forming a first photoresist pattern on a region spaced apart from a region where the conductive pad is located, forming a second photoresist pattern having a lower cross-sectional area greater than an upper cross-sectional area, forming an elastic resin pattern having a lower cross-sectional area greater than an upper cross-sectional area, on a region spaced apart from a region where the conductive pad is located, and forming a conductive wiring pattern covering at least a part of the elastic resin pattern and extending to the conductive pad.

Representative implementations of devices and techniques provide interconnect structures and components for coupling various carriers, printed circuit board (PCB) components, integrated circuit (IC) dice, and the like, using tall and/or fine pitch physical connections. Multiple layers of conductive structures or materials are arranged to form the interconnect structures and components. Nonwettable barriers may be used with one or more of the layers to form a shape, including a pitch of one or more of the layers.

Disclosed are interconnects in which one substrate having a high melting temperature, lead-free solder column is joined to a second substrate having openings filled with a low melting temperature, lead-free solder such that the high melting temperature, lead-free solder column penetrates into the low melting temperature, lead-free solder so as to obtain a short moment arm of solder.

Provided is a method of manufacturing compliant bumps, the method including preparing an electronic device including at least one conductive pad, forming an elastic resin layer on the electronic device, forming a photoresist layer on the elastic resin layer, forming a first photoresist pattern on a region spaced apart from a region where the conductive pad is located, forming a second photoresist pattern having a lower cross-sectional area greater than an upper cross-sectional area, forming an elastic resin pattern having a lower cross-sectional area greater than an upper cross-sectional area, on a region spaced apart from a region where the conductive pad is located, and forming a conductive wiring pattern covering at least a part of the elastic resin pattern and extending to the conductive pad.