The application discloses a light-emitting device including a carrier which includes an insulating layer, an upper conductive layer formed on the insulating layer, a plurality of conducting vias passing through the insulating layer, and a lower conductive layer formed under the insulating layer; four light-emitting elements arranged in rows and columns flipped on the carrier; and a light-passing unit formed on the carrier and covering the four light-emitting elements; wherein each of the light-emitting elements including a first light-emitting bare die emitting a first dominant wavelength, a second light-emitting bare die emitting a second dominant wavelength, and a third light-emitting bare die emitting a third dominant wavelength; and wherein two adjacent first light-emitting bare die in a row has a first distance W1, two adjacent first light-emitting bare die in a column has a second distance W2, and W1 is the same as W2.

The application discloses a light-emitting device including a carrier which includes an insulating layer, an upper conductive layer formed on the insulating layer, a plurality of conducting vias passing through the insulating layer, and a lower conductive layer formed under the insulating layer; four light-emitting elements arranged in rows and columns flipped on the carrier; and a light-passing unit formed on the carrier and covering the four light-emitting elements; wherein each of the light-emitting elements including a first light-emitting bare die emitting a first dominant wavelength, a second light-emitting bare die emitting a second dominant wavelength, and a third light-emitting bare die emitting a third dominant wavelength; and wherein two adjacent first light-emitting bare die in a row has a first distance W1, two adjacent first light-emitting bare die in a column has a second distance W2, and W1 is the same as W2.

A semiconductor device may include a first plate-like element having a first substantially planar connection surface with a first connection pad and a second plate-like element having a second substantially planar connection surface with a second connection pad corresponding to the first connection pad. The device may also include a connection electrically and physically coupling the first and second plate-like elements and arranged between the first and second connection pads. The connection may include a deformed elongate element arranged on the first connection pad and extending toward the second connection pad and solder in contact with the second connection pad and the elongate element.

A semiconductor device may include a first plate-like element having a first substantially planar connection surface with a first connection pad and a second plate-like element having a second substantially planar connection surface with a second connection pad corresponding to the first connection pad. The device may also include a connection electrically and physically coupling the first and second plate-like elements and arranged between the first and second connection pads. The connection may include a deformed elongate element arranged on the first connection pad and extending toward the second connection pad and solder in contact with the second connection pad and the elongate element.

A bonded body includes: a first base body including a first wiring, a first electrode made of an electroplating film and including a first surface having a first region covering a periphery of an end portion of the first wiring and a second region covering the end portion of the first wiring, and a first passivation layer made of an insulating material and covering a periphery of the first electrode; a second base body including a second electrode; and solder disposed between the first region of the first electrode and the second electrode.

A bonded body includes: a first base body including a first wiring, a first electrode made of an electroplating film and including a first surface having a first region covering a periphery of an end portion of the first wiring and a second region covering the end portion of the first wiring, and a first passivation layer made of an insulating material and covering a periphery of the first electrode; a second base body including a second electrode; and solder disposed between the first region of the first electrode and the second electrode.

A fan-out package structure and a manufacturing method thereof are provided. The fan-out package structure includes an upper redistribution layer, a die, a passive element, and an active element. The upper redistribution layer includes a first surface and a second surface opposite to the first surface. The die is disposed on the first surface of the upper redistribution layer and is electrically connected to the upper redistribution layer. The passive element is disposed on the second surface of the upper redistribution layer and is electrically connected to the upper redistribution layer. The active element is disposed on the second surface of the upper redistribution layer and is electrically connected to the upper redistribution layer. The active element is laterally adjacent to the passive element, and the die is electrically connected to the active element and the passive element through the upper redistribution layer.

A semiconductor package includes a package substrate that includes a substrate base and a lower solder resist layer that covers a lower surface of the substrate base, where the lower solder resist layer includes a ponding recess that extends from a lower surface toward an upper surface of the lower solder resist layer, a semiconductor chip attached to an upper surface of the package substrate, an auxiliary chip attached to a lower surface of the package substrate adjacent to the ponding recess through a plurality of chip terminals, where the auxiliary chip includes a first side and a second side opposite to each other in a plane, and an underfill layer that fills a space between the package substrate and the auxiliary chip, surrounds the plurality of chip terminals, and fills the ponding recess.

A package structure is provided. The package structure includes a substrate, a sensor device, an encapsulant and a signal blocking structure. The substrate has a signal passing area. The sensor device is disposed over the substrate. The sensor device has a first surface, a second surface opposite to the first surface and a sensing area located at the second surface. The second surface of the sensor device faces the substrate. The encapsulant covers the sensor device and the substrate. The signal blocking structure extends from the substrate into the encapsulant.

A cryogenic electronic package includes at least two superconducting and/or conventional metal semiconductor structures. Each of the semiconductor structures includes a substrate and a superconducting trace. Additionally, each of the semiconductor structures includes a passivation layer and one or more under bump metal (UBM) structures. The cryogenic electronic package also includes one or more superconducting and/or conventional metal interconnect structures disposed between selected ones of the at least two superconducting semiconductor structures. The interconnect structures are electrically coupled to respective ones of the UBM structures of the semiconductor structures to form one or more electrical connections between the semiconductor structures. A method of fabricating a cryogenic electronic package is also provided.