LTCC structure extends between top and bottom surfaces, with at least one cavity being formed within the structure and extending from the top surface inwardly in the direction of the bottom surface. A die is disposed within the cavity a top surface of the die is positioned flush with the top surface of the package, resulted in the shortest length of the wire box connecting the die with the LTCC structure and ultimately reducing the inductance.

A semiconductor package includes an insulating layer including a first face and a second face opposite each other, a redistribution pattern including a wiring region and a via region in the insulating layer, the wiring region being on the via region, and a first semiconductor chip connected to the redistribution pattern. The first semiconductor chip may be on the redistribution pattern. An upper face of the wiring region may be coplanar with the first face of the insulating layer.

Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes a first semiconductor chip including a first substrate and a first conductive feature formed over the first substrate, and a second semiconductor chip bonded to the first semiconductor chip. The second semiconductor chip includes a second substrate and a second conductive feature formed over the second substrate. A conductive plug is disposed through the first conductive feature and is coupled to the second conductive feature. The conductive plug includes a first portion disposed over the first conductive feature, the first portion having a first width, and a second portion disposed beneath or within the first conductive feature. The second portion has a second width. The first width is greater than the second width.

Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes a first semiconductor chip including a first substrate and a first conductive feature formed over the first substrate, and a second semiconductor chip bonded to the first semiconductor chip. The second semiconductor chip includes a second substrate and a second conductive feature formed over the second substrate. A conductive plug is disposed through the first conductive feature and is coupled to the second conductive feature. The conductive plug includes a first portion disposed over the first conductive feature, the first portion having a first width, and a second portion disposed beneath or within the first conductive feature. The second portion has a second width. The first width is greater than the second width.

A die includes a substrate, a conductive pad, a connector and a protection layer. The conductive pad is disposed over the substrate. The connector is disposed on the conductive pad. The connector includes a seed layer and a conductive post. The protection layer laterally covers the connector. Topmost surfaces of the seed layer and the conductive post and a top surface of the protection layer are level with each other.

A semiconductor device includes a support substrate with leads arranged therearound, a semiconductor die on the support substrate, and a layer of laser-activatable material molded onto the die and the leads. The leads include proximal portions facing towards the support substrate and distal portions facing away from the support substrate. The semiconductor die includes bonding pads at a front surface thereof which is opposed to the support substrate, and is arranged onto the proximal portions of the leads. The semiconductor device has electrically-conductive formations laser-structured at selected locations of the laser-activatable material. The electrically-conductive formations include first vias extending between the bonding pads and a front surface of the laser-activatable material, second vias extending between the distal portions of the leads and the front surface of the laser-activatable material, and lines extending at the front surface of the laser-activatable material and connecting selected first vias to selected second vias.

Vertical etch heterolithic integrated circuit devices are described. A method of manufacturing NIP diodes is described in one example. A P-type substrate is provided, and an intrinsic layer is formed on the P-type substrate. An oxide layer is formed on the intrinsic layer, and one or more openings are formed in the oxide layer. One or more N-type regions are implanted in the intrinsic layer through the openings in the oxide layer. The N-type regions form cathodes of the NIP diodes. A dielectric layer deposited over the oxide layer is selectively etched away with the oxide layer to expose certain ranges of the intrinsic layer to define a geometry of the NIP diodes. The intrinsic layer and the P-type substrate are vertically etched away within the ranges to expose sidewalls of the intrinsic layer and the P-type substrate. The P-type substrate forms the anodes of the NIP diodes.

An integrated circuit packaging method and an integrated packaging circuit, the integrated circuit packaging method including: circuit layers are provided on the top surface of a substrate, the bottom surface of the substrate or the interior of the substrate, the circuit layers having circuit pins; the substrate is provided with connection through holes, and the connection through holes are joined up with the circuit pins; a device is placed on the substrate, and the device is provided with device pins on a surface facing the substrate, which makes the device pins join up with a first opening of the connection through holes; conductive layers are fabricated in the connection through holes by means of a second opening of the connection through holes; and the conductive layers electrically connect the device pins to the circuit pins.

A chip package and method for fabricating the same are provided that includes an off-die inductor. The off-die inductor is disposed in a redistribution layer formed on a bottom surface of an integrated circuit (IC) die. The redistribution layer is connected to a package substrate to form the chip package.

A manufacturing method of a semiconductor structure includes covering first and second semiconductor dies with an insulating encapsulant. The first semiconductor die includes an active surface accessibly exposed by the insulating encapsulant and a first conductive terminal distributed at the active surface. The second semiconductor die includes an active surface accessibly exposed by the insulating encapsulant and a second conductive terminal distributed at the active surface. A redistribution circuit layer is formed on the insulating encapsulant and the active surfaces of the first and second semiconductor dies. A conductive trace of the redistribution circuit layer is electrically connected from the first semiconductor die and meanderingly extends to the second semiconductor die, and a ratio of a total length of the conductive trace to a top width of the insulating encapsulant between the first and second semiconductor dies ranges from about 3 to about 10.