Patent classifications
H01L2224/26155
Light emitting device
A light emitting device includes a substrate and a light emitting element mounted on the substrate, a light transmissive member, covering member, first and second protruding members, and a protective element. The light transmissive member is disposed on an upper surface of the light emitting element. The covering member covers an upper surface of the substrate, a lateral surface of the light emitting element, and at least a portion of a lateral surface of the light transmissive member such that an upper surface of the light transmissive member is exposed. The first protruding member and the second protruding member are provided on the substrate such that the light emitting element and the light transmissive member are positioned between the first protruding member and the second protruding member. The protective element is mounted on the substrate so as to be positioned between the light emitting element and the second protruding member.
POWER SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR POWER SEMICONDUCTOR DEVICE
A power semiconductor device includes a substrate and a semiconductor element bonded onto a first surface of the substrate through use of a sintered metal bonding material. The substrate has a plurality of dimples formed in the first surface and located outside a location immediately below a heat generation unit of the semiconductor element. The sintered metal bonding material is supplied onto the substrate after the formation of the dimples, and the semiconductor element is bonded to the substrate through application of heat and a pressure thereto.
DIE ATTACHED LEVELING CONTROL BY METAL STOPPER BUMPS
In some embodiments, the present disclosure relates to an integrated chip (IC), including a substrate, a first die disposed over the substrate, a metal wire attached to a frontside of the first die, and a first plurality of die stopper bumps disposed along a backside of the first die and configured to control an angle of operation of the first die. The first plurality of die stopper bumps directly contacts a backside surface of the first die.
EMI CAGE FOR MICROSTRIP ROUTING VIA DUAL LAYER UNDERFILL CONCEPT
Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a package substrate, and a die coupled to the package substrate. In an embodiment, a stiffener is around the die and over the package substrate. In an embodiment, an electrically non-conductive underfill is around first level interconnects (FLIs) between the package substrate and the die. In an embodiment, an electrically conductive layer is around the non-conductive underfill.
DISPLAY STRUCTURE AND MANUFACTRUING METHOD THEREOF
A display structure and a manufacturing method thereof are provided. The display structure includes a substrate, a display component layer, an insulating protective layer, a plurality of display signal lines, a plurality of first connecting pads and a flip-chip thin-film package, wherein the first connecting pads are disposed on a back surface of the substrate, and connected with the display signal lines; the flip-chip thin-film package has a plurality of second connecting pads electrically connecting to the first connecting pads. The connecting pads disposed on the flip-chip thin-film package are connecting to the connecting pads disposed on the back surface of the display panel, so that achieve no need to bend the display, thereby increasing a screen ratio of the display.
PROCESS FOR MANUFACTURING A STRAINED SEMICONDUCTOR DEVICE AND CORRESPONDING STRAINED SEMICONDUCTOR DEVICE
A process for manufacturing a strained semiconductor device envisages: providing a die of semiconductor material, in which elementary components of the semiconductor device have been integrated by means of initial front-end steps; and coupling, using the die-attach technique, the die to a support, at a coupling temperature. The aforesaid coupling step envisages selecting the value of the coupling temperature at a value higher than an operating temperature of use of the semiconductor device, and moreover selecting the material of the support so that it is different from the material of the die in order to determine, at the operating temperature, a coupling stress that is a function of the different values of the coefficients of thermal expansion of the materials of the die and of the support and of the temperature difference between the coupling temperature and the operating temperature. Furthermore, additional stress can be enhanced by means of different embodiments involving the support, such as ring or multi-layer frame.
Packaged semiconductor devices and methods of packaging thereof
Packaging methods for semiconductor devices and methods of packaging thereof are disclosed. In some embodiments, a device includes a packaging apparatus and contact pads disposed on the packaging apparatus. The contact pads are arranged in an array of rows and columns. The contact pads include first contact pads proximate a perimeter region of the packaging apparatus and second contact pads disposed in an interior region of the packaging apparatus. A dam structure that is continuous is disposed around the second contact pads. The contact pads comprise a mounting region for a semiconductor device.
Process for manufacturing a strained semiconductor device and corresponding strained semiconductor device
A process for manufacturing a strained semiconductor device envisages: providing a die of semiconductor material, in which elementary components of the semiconductor device have been integrated by means of initial front-end steps; and coupling, using the die-attach technique, the die to a support, at a coupling temperature. The aforesaid coupling step envisages selecting the value of the coupling temperature at a value higher than an operating temperature of use of the semiconductor device, and moreover selecting the material of the support so that it is different from the material of the die in order to determine, at the operating temperature, a coupling stress that is a function of the different values of the coefficients of thermal expansion of the materials of the die and of the support and of the temperature difference between the coupling temperature and the operating temperature. Furthermore, additional stress can be enhanced by means of different embodiments involving the support, such as ring or multi-layer frame.
Integrated Circuit Package and Method
In an embodiment, a device includes: an integrated circuit die; a redistribution structure over a front-side surface of the integrated circuit die; a socket over the redistribution structure; a mechanical brace over the socket, the mechanical brace having an opening exposing the socket, edge regions of the socket overlapping edge regions of the mechanical brace at the opening; a first standoff screw disposed in the edge regions of the mechanical brace, the first standoff screw physically contacting the socket, the first standoff screw extending a first distance between the socket and the mechanical brace; and a bolt extending through the mechanical brace and the redistribution structure.
DISPLAY PANEL COMPRISING MICRO LIGHT-EMITTING DIODES AND METHOD FOR MAKING SAME
A micro LED display panel includes a substrate, a plurality of first metal electrodes and a plurality of metal pads on a surface of the substrate, a connection layer on the substrate, a plurality of micro LEDs on a side of the connection layer away from the substrate. The connection layer includes conductive particles. Each of the micro LEDs is coupled to at least one of the first metal electrode. A side of each of the metal pads away from the substrate is coupled to some of the conductive particles in the connection layer to form a metal retaining wall. The metal retaining walls enhance structural strength of the micro LED display panel and avoid breakage of any of the micro LEDs.