In an embodiment, a device includes: an integrated circuit die; a redistribution structure over a front-side surface of the integrated circuit die; a socket over the redistribution structure; a mechanical brace over the socket, the mechanical brace having an opening exposing the socket, edge regions of the socket overlapping edge regions of the mechanical brace at the opening; a first standoff screw disposed in the edge regions of the mechanical brace, the first standoff screw physically contacting the socket, the first standoff screw extending a first distance between the socket and the mechanical brace; and a bolt extending through the mechanical brace and the redistribution structure.

A chip package structure is provided. The chip package structure includes a substrate. The chip package structure includes a chip over the substrate. The chip package structure includes a first bump and a first dummy bump between the chip and the substrate. The first bump is electrically connected between the chip and the substrate, the first dummy bump is electrically insulated from the substrate, the first dummy bump is between the first bump and a corner of the chip, and the first dummy bump is wider than the first bump.

A method that includes providing a substrate having first and second regions for forming first and second light emitting devices, respectively, that are axisymmetrical in plan view with respect to a boundary line extending between the regions. The method includes mounting first and second light emitting elements in the first and second regions, respectively, arranging first and second light transmissive members respectively thereon, and arranging a covering member to collectively cover at least a portion of the first and second light emitting devices. The first and second devices have external connection terminals that are exposed. The terminals of the first light emitting device are on a side of the first light emitting device opposite to a side thereof adjacent the boundary line, and the terminals of the second light emitting device are on a side thereof opposite to a side of the second light emitting device adjacent the boundary line.

A light emitting device includes a substrate and a light emitting element mounted on the substrate, a light transmissive member, covering member, first and second protruding members, and a protective element. The light transmissive member is disposed on an upper surface of the light emitting element. The covering member covers an upper surface of the substrate, a lateral surface of the light emitting element, and at least a portion of a lateral surface of the light transmissive member such that an upper surface of the light transmissive member is exposed. The first protruding member and the second protruding member are provided on the substrate such that the light emitting element and the light transmissive member are positioned between the first protruding member and the second protruding member. The protective element is mounted on the substrate so as to be positioned between the light emitting element and the second protruding member.

Embodiments include semiconductor packages and method of forming the semiconductor packages. A semiconductor package includes first waveguides over a package substrate. The first waveguides include first angled conductive layers, first transmission lines, and first cavities. The semiconductor package also includes a first dielectric over the first waveguides and package substrate, second waveguides over the first dielectric and first waveguides, and a second dielectric over the second waveguides and first dielectric. The second waveguides include second angled conductive layers, second transmission lines, and second cavities. The first angled conductive layers are positioned over the first transmission lines and package substrate having a first pattern of first triangular structures. The second angled conductive layers are positioned over the second transmission lines and first dielectric having a second pattern of second triangular structures, where the second pattern is shaped as a coaxial interconnects enclosed with second triangular structures and portions of first dielectric.

Semiconductor packaging substrates and processing sequences are described. In an embodiment, a packaging substrate includes a build-up structure, and a patterned metal contact layer partially embedded within the build-up structure and protruding from the build-up structure. The patterned metal contact layer may include an array of surface mount (SMT) metal bumps in a chip mount area, a metal dam structure or combination thereof.

A method for forming a chip package structure is provided. The method includes bonding a chip to a first surface of a first substrate. The method includes forming a bump and a dummy bump over a second surface of the first substrate. The dummy bump is close to a first corner of the first substrate, and the dummy bump is wider than the bump. The method includes bonding the first substrate to a second substrate through the bump. The dummy bump is electrically insulated from the chip and the second substrate. The method includes forming a protective layer between the first substrate and the second substrate. The protective layer surrounds the dummy bump and the bump, and the protective layer is between the dummy bump and the second substrate.

A light emitting device includes a substrate, light emitting elements, light transmissive members, an underfill, and a cover member. The light emitting elements are mounted on the substrate. The light transmissive members are each disposed on an upper surface of each of the light emitting elements. The underfill covers an upper surface of the substrate, lateral surfaces of the light emitting elements, and lateral surfaces of the light transmissive members between the light transmissive members. The cover member covers an upper surface of the underfill and has a hardness greater than a hardness of the underfill.

A power semiconductor device includes a substrate and a semiconductor element bonded onto a first surface of the substrate through use of a sintered metal bonding material. The substrate has a plurality of dimples formed in the first surface and located outside a location immediately below a heat generation unit of the semiconductor element. The sintered metal bonding material is supplied onto the substrate after the formation of the dimples, and the semiconductor element is bonded to the substrate through application of heat and a pressure thereto.

A method for forming a chip package structure is provided. The method includes bonding a chip to a first surface of a first substrate. The method includes forming a bump and a dummy bump over a second surface of the first substrate. The dummy bump is close to a first corner of the first substrate, and the dummy bump is wider than the bump. The method includes bonding the first substrate to a second substrate through the bump. The dummy bump is electrically insulated from the chip and the second substrate. The method includes forming a protective layer between the first substrate and the second substrate. The protective layer surrounds the dummy bump and the bump, and the protective layer is between the dummy bump and the second substrate.