To provide a sheet for sintering bonding and a sheet for sintering bonding with a base material that are suited for being made with a good operational efficiency and that are also suited for realizing a satisfactory operational efficiency in a sintering process in a process of producing a semiconductor device that goes through sintering bonding of semiconductor chips. A sheet for sintering bonding 10 of the present invention comprises an electrically conductive metal containing sinterable particle and a binder component, and has a shear strength at 23 C. of 2 to 40 MPa measured in accordance with a SAICAS method. A sheet body X, which is a sheet for sintering bonding with a base material according to the present invention, has a laminated structure comprising a base material B and the sheet for sintering bonding 10.

A sheet for sintering bonding 10 of the present invention comprises an electrically conductive metal containing sinterable particle and a binder component, and upon subjecting the sheet to a pressurization treatment onto a silver plane of a 5 mm square Si chip under predetermined conditions, the ratio of the area of a layer of a material for sintering bonding transferred onto the silver plane to the silver plane area is 0.75 to 1. A sheet body X of the present invention has a laminated structure comprising a base material B and the sheet 10. A semiconductor chip with a layer of a material for sintering bonding of the present invention comprises a semiconductor chip and a material layer derived from the sheet 10 on one face of the chip, and the ratio of the area of the material layer to the area of that face is 0.75 to 1.

A wafer-level packaging method and a package structure are provided. In the method, a first wafer is provided having first chips formed there-in. A surface of each first chip is integrated with a first electrode. A first dielectric layer is formed on the first wafer to expose each first electrode. Second chips are provided with a surface of each second chip integrated with a second electrode. A second dielectric layer is formed on the plurality of second chips to expose each second electrode. The second dielectric layer is positioned relative to the first dielectric layer. The second chips are bonded to the first wafer with each second chip aligned relative to one first chip to form a cavity there-between. A chip interconnection structure is formed in the cavity to electrically connect the first electrode with the second electrode. An encapsulation layer covers the second chips.

Molded air cavity packages and methods for producing molded air cavity packages are disclosed. In one embodiment, the molded air cavity package includes a molded package body having an upper peripheral edge portion, an air cavity around which the upper peripheral edge portion extends, and a cover piece bonded to the upper peripheral edge portion to enclose the air cavity. The cover piece has a lower peripheral edge portion, which cooperates with the upper peripheral edge portion to define a cover-body interface. The cover-body interface includes an annular channel extending around the cover-body interface, as taken about the package centerline, and first and second hardstop features formed on the upper peripheral edge portion of the molded package body and on the lower peripheral edge portion of the cover piece, respectively. The hardstop features contact to determine a vertical height of the annular channel, as taken along the package centerline.

Provided are a sintered material excellent in both thermal stress and bonding strength; a connection structure comprising the sintered material; a composition for bonding with which the sintered material can be produced; and a method for producing the sintered material. The sintered material comprises a base portion, one or more buffer portions, and one or more filling portions. The buffer portions and the filling portions are dispersed in the base portion. The base portion is a metal sintered body, each buffer portion is formed from at least one of a pore and a material that is not the same as that of the sintered body, and each filling portion is formed from at least one of particles and fibers. The sintered material satisfies A>B, where A is the kurtosis of volume distribution of the base portions in a three-dimensional image of the sintered material, and B is the kurtosis of volume distribution of the base portions in a three-dimensional image of the sintered material from which the filling portions are removed.

Provided are a sintered material excellent in both thermal stress and bonding strength; a connection structure comprising the sintered material; a composition for bonding with which the sintered material can be produced; and a method for producing the sintered material. The sintered material comprises a base portion, one or more buffer portions, and one or more filling portions. The buffer portions and the filling portions are dispersed in the base portion. The base portion is a metal sintered body, each buffer portion is formed from at least one of a pore and a material that is not the same as that of the sintered body, and each filling portion is formed from at least one of particles and fibers. The sintered material satisfies A>B, where A is the kurtosis of volume distribution of the base portions in a three-dimensional image of the sintered material, and B is the kurtosis of volume distribution of the base portions in a three-dimensional image of the sintered material from which the filling portions are removed.

A method of manufacturing a semiconductor device includes: applying a bonding resin composition on a semiconductor chip supporting member, the bonding resin composition containing a thermosetting resin and silver microparticles having an average particle size of 10 to 200 nm, the silver microparticles having a protective layer made of an organic compound on surfaces thereof; a semi-sintering step of heating the applied bonding resin composition at a temperature that is lower than a reaction starting temperature of the thermosetting resin and is equal to or more than 50 C. to bring the silver microparticles into a semi-sintered state; and a bonding step including: placing a semiconductor chip on the bonding resin composition containing the silver microparticles in a semi-sintered state, heating at a temperature higher than the reaction starting temperature of the thermosetting resin in a pressure-free state, and bonding the semiconductor chip to the semiconductor chip supporting member.

A semiconductor device of the present invention includes a circuit layer formed of a conductive material, a semiconductor element mounted on a first surface of the circuit layer, and a ceramic substrate disposed on a second surface of the circuit layer, in which a Ag underlayer having a glass layer and a Ag layer laminated on the glass layer is formed on the first surface of the circuit layer, and the Ag layer of the Ag underlayer and the semiconductor element are directly joined together.

A semiconductor device of the present invention includes a circuit layer formed of a conductive material, a semiconductor element mounted on a first surface of the circuit layer, and a ceramic substrate disposed on a second surface of the circuit layer, in which a Ag underlayer having a glass layer and a Ag layer laminated on the glass layer is formed on the first surface of the circuit layer, and the Ag layer of the Ag underlayer and the semiconductor element are directly joined together.

A power module includes: a plate-shaped thick copper substrate, a conductive stress relaxation metal layer disposed on the thick copper substrate, a semiconductor device disposed on the stress relaxation metal layer, and a plated layer disposed on the stress relaxation metal layer, wherein the semiconductor device is bonded to the stress relaxation metal layer via the plated layer. The thick copper substrate includes a first thick copper layer and a second thick copper layer disposed on the first thick copper layer, and the stress relaxation metal layer is disposed on the second thick copper layer. A part of the semiconductor device is embedded to be fixed to the stress relaxation metal layer. A bonded surface between the semiconductor device and the stress relaxation metal layer are integrated to each other by means of diffusion bonding or solid phase diffusion bonding.