A wafer-level packaging method includes providing a base substrate and providing first chips. A photolithographic bonding layer is formed on the base substrate or on the first chips. First vias are formed in the photolithographic bonding layer. The first chips are pre-bonded to the base substrate through a photolithographic bonding layer with each first chip corresponding to a first via. A thermal compression bonding process is used to bond the first chips to the base substrate such that an encapsulation material fills between adjacent first chips and covers the first chips and the base substrate. The base substrate is etched to form second vias through the base substrate with each second via connected to a first via to form a first conductive via. A first conductive plug is formed in the first conductive via to electrically connect to a corresponding first chip.

The present disclosure relates to micro-LED chips, methods for manufacturing the same, and display devices. The micro-LED chip includes: a driving backplane including at least one first electrode, a groove being provided above the first electrode, and the first electrode being located at a bottom of the groove; the groove being filled with a conductive material, and the conductive material being obtained by curing a corresponding conductive ink; and a light emitting chip including at least one second electrode; and the first electrode is connected to the second electrode through the conductive material.

An electro-optic assembly includes a layer of electro-optic material configured to switch optical states upon application of an electric field and an anisotropically conductive layer having one or more moisture-resistive polymers and a conductive material, the moisture-resistive polymer having a WVTR less than 5 g/(m.sup.2*d).

A manufacturing method of a device chip includes a die bonding resin providing step of supplying a die bonding resin in a liquid state to a back surface side of a wafer with device chips formed on a front surface thereof and solidifying the die bonding resin, a water-soluble resin providing step of covering the die bonding resin with a water-soluble resin, a laser processing step of applying a laser beam from the back surface side of the wafer to remove the die bonding resin and the water-soluble resin, an etching step of etching an exposed portion on the back surface side of the wafer to divide the wafer, and a water-soluble resin removing step of supplying water on the back surface side of the wafer to remove the water-soluble resin.

A method of manufacturing a semiconductor package includes preparing a wafer having a first surface on which a plurality of semiconductor chips are disposed and a second surface, opposite to the first surface. The second surface of the wafer is ground. The ground second surface of the wafer is coated with a liquid adhesive material to form an uncured adhesive layer having a thickness of 5 m or less. The uncured adhesive layer on the wafer is semi-cured. The wafer is cut so as to separate the plurality of semiconductor chips from one another. The plurality of semiconductor chips are stacked using the semi-cured adhesive layer. The semi-cured adhesive layer disposed between the plurality of stacked semiconductor chips is fully cured.

A wafer-level packaging method using a photolithographic bonding material includes providing a base substrate; providing a plurality of first chips; forming a photolithographic bonding layer on the base substrate or on the first chips; forming a plurality of first vias in the photolithographic bonding layer; pre-bonding the first chips to the base substrate through the photolithographic bonding layer with each first chip corresponding to a first via; using a thermal compression bonding process to bond the first chips to the base substrate such that an encapsulation material fills between adjacent first chips and covers the first chips and the base substrate; etching the base substrate to form a plurality of second vias through the base substrate with each second via connected to a first via to form a first conductive via; and forming a first conductive plug in the first conductive via to electrically connect to a corresponding first chip.

A thermal interface material and systems and methods for forming a thermal interface material include depositing a layer of a composite material, including at least a first material and a second material, the first material including a carrier fluid and the second material including a filler particle suspended within the first material. A particle manipulator is positioned over the layer of the composite material, the particle manipulator including at least one emitter to apply a particle manipulating field to bias a movement of the filler particles. The second material is redistributed by applying the particle manipulating field to interact with the second material causing the second material to migrate from a surrounding region in the composite material into a high concentration region in the composite material to form a customized thermal interface such that the high concentration region is configured and positioned corresponding to a hotspot.

Embodiments relate to forming nanoporous contacts on a receiving substrate without using a seed layer on the receiving substrate. The nanoporous contacts can be used to create bonds between electronic components and the receiving substrate. To form the contacts, a photoresist mask is created on the receiving substrate by a photolithographic process. Through a sputtering process, portions of co-alloy on a depositing substrate are transferred to the receiving substrate with the photoresist mask. The photoresist mask is removed from the receiving substrate. The remaining co-alloy portions on the receiving substrate undergo a de-alloying process to form an array of nanoporous contacts.

Disclosed are exemplary embodiments of compressible foamed thermal interface materials. Also disclosed are methods of making and using compressible foamed thermal interface materials.

A package structure includes a first RDL, an adhesive layer and a first electronic component. Upper bumps and conductive pads are provided on a first upper surface and a first lower surface of the first RDL, respectively. The adhesive layer is located on the first upper surface of the first RDL and surrounds the upper bumps. The first electronic component is mounted on the adhesive layer and includes conductors which are visible from an active surface of the first electronic component and joined to the upper bumps, the active surface of the first electronic component faces toward the first upper surface of the first RDL. Two adhesive surfaces of the adhesive layer are adhered to the first upper surface of the first RDL and the active surface of the first electronic component, respectively.