An apparatus comprising a first substrate, a dam structure disposed on a first side of the first substrate, and an integrated circuit (IC) memory chip coupled to the first side of the first substrate by a plurality of first conductive members. A second substrate is coupled to a second side of the first substrate by a plurality of second conductive members. A lid coupled to the second substrate encloses the IC memory chip and the first substrate. A thermal interface material (TIM) is coupled between the lid and the dam structure.

An apparatus comprising a first substrate, a dam structure disposed on a first side of the first substrate, and an integrated circuit (IC) memory chip coupled to the first side of the first substrate by a plurality of first conductive members. A second substrate is coupled to a second side of the first substrate by a plurality of second conductive members. A lid coupled to the second substrate encloses the IC memory chip and the first substrate. A thermal interface material (TIM) is coupled between the lid and the dam structure.

The present invention relates to a method of manufacturing a power device and a structure of the power device, which is used to solve the problem that conventional power device needs to be independently packaged and requires a welding process. The method includes: forming a plurality of semiconductor device layers spaced in intervals on a front of a silicon wafer; excavating a plurality of grooves on the front of the silicon wafer to separate the plurality of semiconductor device layers; filling each of the plurality of grooves with each of a plurality of first spacer materials; grinding a back of the silicon wafer until the first spacer materials being exposed; attaching a plurality of metal layers to a region of the back of the silicon wafer opposite to the plurality of semiconductor device layers; and electrically connecting each of independent plurality of lead frames to the plurality of metal layers respectively. The present invention further includes the structure of the power device.

A system for applying materials to components generally includes a tool operable for transferring a portion of a material from a supply of the material to a component. The tool may include a resilient material configured for tamping the portion of the material onto the component and imprinting the portion of the material for release and transfer from the supply.

The present invention relates to a method of manufacturing a power device and a structure of the power device, which is used to solve the problem that conventional power device needs to be independently packaged and requires a welding process. The method includes: forming a plurality of semiconductor device layers spaced in intervals on a front of a silicon wafer; excavating a plurality of grooves on the front of the silicon wafer to separate the plurality of semiconductor device layers; filling each of the plurality of grooves with each of a plurality of first spacer materials; grinding a back of the silicon wafer until the first spacer materials being exposed; attaching a plurality of metal layers to a region of the back of the silicon wafer opposite to the plurality of semiconductor device layers; and electrically connecting each of independent plurality of lead frames to the plurality of metal layers respectively. The present invention further includes the structure of the power device.

An apparatus comprising a first substrate, a dam structure disposed on a first side of the first substrate, and an integrated circuit (IC) memory chip coupled to the first side of the first substrate by a plurality of first conductive members. A second substrate is coupled to a second side of the first substrate by a plurality of second conductive members. A lid coupled to the second substrate encloses the IC memory chip and the first substrate. A thermal interface material (TIM) is coupled between the lid and the dam structure.

An apparatus comprising a first substrate, a dam structure disposed on a first side of the first substrate, and an integrated circuit (IC) memory chip coupled to the first side of the first substrate by a plurality of first conductive members. A second substrate is coupled to a second side of the first substrate by a plurality of second conductive members. A lid coupled to the second substrate encloses the IC memory chip and the first substrate. A thermal interface material (TIM) is coupled between the lid and the dam structure.

Embodiments herein describe techniques for bonded wafers that includes a first wafer bonded with a second wafer, and a stress compensation layer in contact with the first wafer or the second wafer. The first wafer has a first stress level at a first location, and a second stress level different from the first stress level at a second location. The stress compensation layer includes a first material at a first location of the stress compensation layer that induces a third stress level at the first location of the first wafer, a second material different from the first material at a second location of the stress compensation layer that induces a fourth stress level different from the third stress level at the second location of the first wafer. Other embodiments may be described and/or claimed.

Embodiments herein describe techniques for bonded wafers that includes a first wafer bonded with a second wafer, and a stress compensation layer in contact with the first wafer or the second wafer. The first wafer has a first stress level at a first location, and a second stress level different from the first stress level at a second location. The stress compensation layer includes a first material at a first location of the stress compensation layer that induces a third stress level at the first location of the first wafer, a second material different from the first material at a second location of the stress compensation layer that induces a fourth stress level different from the third stress level at the second location of the first wafer. Other embodiments may be described and/or claimed.

A method for manufacturing a die attach film includes forming a plurality of posts on a support sheet. The method includes forming an adhesive layer between the posts. A thermal conductivity of the adhesive layer is lower than a thermal conductivity of the posts. The method includes removing the support sheet.