A semiconductor device of the present invention includes a circuit layer formed of a conductive material, a semiconductor element mounted on a first surface of the circuit layer, and a ceramic substrate disposed on a second surface of the circuit layer, in which a Ag underlayer having a glass layer and a Ag layer laminated on the glass layer is formed on the first surface of the circuit layer, and the Ag layer of the Ag underlayer and the semiconductor element are directly joined together.

A packaging method and a package structure for a fingerprint recognition chip and a drive chip are provided. The packaging method is a wafer-level packaging method. According to the method, a blind hole is formed on the back surface of a wafer and the drive chip is secured in the blind hole, then the wafer is cut to obtain a package structure for the fingerprint recognition chip and the drive chip. In this way, the drive chip is packaged in the back surface of the wafer-level fingerprint recognition chip, thereby reducing the complexity of the package process. In addition, the size of the package structure is close to the size of the single fingerprint recognition chip, thereby greatly reducing the size of the package structure and improving the integration of the package structure.

The present disclosure relates to a method for bonding semiconductor components. A semiconductor component comprising microbumps on a planar bonding surface is prepared for bonding by applying a photosensitive polymer layer on the bonding surface. The average thickness of the initial polymer layer in between the microbumps is similar to the average height of the microbumps. In a lithography process, the polymer is removed from the upper surface of the microbumps and from areas around the microbumps. The polymer is heated to a temperature at which the polymer flows, resulting in a polymer layer that closely adjoins the microbumps, without exceeding the microbump height. The closely adjoining polymer layer may have a degree of planarity substantially similar to a planarized layer.

A method may include providing a chip carrier having a chip supporting region to support a chip, and a chip contacting region having at least one contact pad, the chip carrier being thinner in the chip contacting region such that a first thickness of the chip carrier at the at least one contact pad is smaller than a second thickness of the chip carrier in the chip supporting region. A disposing of the chip, having at least one contact protrusion, over the chip carrier, such that the at least one contact protrusion is arranged over the at least one contact pad may be included. In addition, a pressing of the chip against the chip carrier such that the at least one contact protrusion extends at least partially into the chip contacting region and is electrically contacted to the at least one contact pad may be included.

A method may include providing a chip carrier having a chip supporting region to support a chip, and a chip contacting region having at least one contact pad, the chip carrier being thinner in the chip contacting region such that a first thickness of the chip carrier at the at least one contact pad is smaller than a second thickness of the chip carrier in the chip supporting region. A disposing of the chip, having at least one contact protrusion, over the chip carrier, such that the at least one contact protrusion is arranged over the at least one contact pad may be included. In addition, a pressing of the chip against the chip carrier such that the at least one contact protrusion extends at least partially into the chip contacting region and is electrically contacted to the at least one contact pad may be included.

Highly reliable chip mounting is accomplished by using a substrate having such a shape that a stress exerted on a flip-chip-connected chip can be reduced, so that the stress exerted on the chip is reduced and separation of an interlayer insulating layer having a low dielectric constant (low-k) is minimized. Specifically, in a chip mounting structure, a chip including an interlayer insulating layer having a low dielectric constant (low-k) is flip-chip connected to a substrate via bumps is shown. In the chip mounting structure, the substrate has such a shape that a mechanical stress exerted on the interlayer insulating layer at corner portions of the chip due to a thermal stress is reduced, the thermal stress occurring due to a difference in coefficient of thermal expansion between the chip and the substrate.

A joined structure which is configured such that a space between adjacent substrates is filled with a filling material. The joined structure includes a first substrate having a first conductor formed on a surface of the first substrate, a second substrate having a second conductor formed on a surface of the second substrate, arranged so that a surface of the first substrate faces a surface of the second substrate, a connecting conductor which electrically connects the first conductor and the second conductor, and a filling material between the first substrate and the second substrate. The filling material is formed into such a shape that a space is provided which corresponds to at least one of the first conductor, the second and the connecting conductor.

A semiconductor device includes a semiconductor substrate, a TiW layer arranged on the semiconductor substrate a Ti layer arranged on the TiW layer, a Ni alloy layer arranged on the Ti layer, and an Ag layer arranged on the Ni alloy layer, wherein the Ag layer and the Ni alloy layer comprise side faces fabricated by at least one wet etching process, and wherein the Ti layer and the TiW layer comprise side faces fabricated by a dry etching process.

An optical sensor module includes a transparent lid spaced apart from the optical sensor die by a protective dam. The dam can be formed by photosensitive epoxy materials that can be patterned using a photolithography process. The epoxy materials can change between liquid and solid phases during assembly, and then can be fully hardened by curing. The protective dam can be formed as a single layer, or as a multi-layer stack of epoxy materials, in which the layers may have different properties. In some implementations, the epoxy dam acts as a spacer that provides a substantially uniform gap to minimize a tilt angle of the transparent lid with respect to the optical sensor.

The present invention relates to a production process for a solder electrode, including: a step (1) of forming a coating film of a photosensitive resin composition on a substrate having an electrode pad; a step (2) of forming resist having an opening in a region corresponding to the electrode pad by selectively exposing the coating film to light and further developing the film; and a step (3) of filling the opening with molten solder, in which the photosensitive resin composition contains at least a benzoxazole precursor. According to the production process for the solder electrode of the present invention, development of cracks on a resist surface can be prevented, and solder filling capability can be improved, even when the resist receives high heat during solder filling as in an IMS method, and therefore the solder electrode adapted for the purpose can be appropriately produced.