A method of and system for adhesive bonding. The method and system a) treat a surface of an element to be bonded to provide an adherent structure including one or more rubber compounds on the surface; b) place a polymerizable adhesive composition, including at least one photoinitiator and at least one energy converting material, in contact with the adherent structure and two or more components to be bonded to form an assembly, c) irradiated the assembly with radiation at a first wavelength, capable of conversion by the at least one energy converting material, to a second wavelength capable of activating the at least one photoinitiator to produce from the polymerizable adhesive composition a cured adhesive composition; and d) adhesively join the two or more components by way of the adherent structure and the cured adhesive composition.

A method of and system for adhesive bonding. The method and system a) treat a surface of an element to be bonded to provide an adherent structure including one or more rubber compounds on the surface; b) place a polymerizable adhesive composition, including at least one photoinitiator and at least one energy converting material, in contact with the adherent structure and two or more components to be bonded to form an assembly, c) irradiated the assembly with radiation at a first wavelength, capable of conversion by the at least one energy converting material, to a second wavelength capable of activating the at least one photoinitiator to produce from the polymerizable adhesive composition a cured adhesive composition; and d) adhesively join the two or more components by way of the adherent structure and the cured adhesive composition.

According to various embodiments, a chip carrier may include: a chip supporting region configured to support a chip; a chip contacting region including at least one contact pad for electrically contacting the chip; wherein the chip carrier is thinned in the chip contacting region such that a first thickness of the chip carrier at the at least one contact pad is smaller than a second thickness of the chip carrier in the chip supporting region.

According to various embodiments, a chip carrier may include: a chip supporting region configured to support a chip; a chip contacting region including at least one contact pad for electrically contacting the chip; wherein the chip carrier is thinned in the chip contacting region such that a first thickness of the chip carrier at the at least one contact pad is smaller than a second thickness of the chip carrier in the chip supporting region.

An electronic device includes a drive substrate (a pressure chamber substrate and a vibration plate) including a piezoelectric element and electrode wirings related to driving of the piezoelectric element formed thereon, and a sealing plate bonded thereto, the electrode wirings are made of wiring metal containing gold (Au) on the drive substrate through an adhesion layer which is a base layer, and has a removed portion in which a portion of the wiring metal in a region containing a part bonded to a bonding resin is removed and the adhesion layer is exposed.

An electronic device includes a drive substrate (a pressure chamber substrate and a vibration plate) including a piezoelectric element and electrode wirings related to driving of the piezoelectric element formed thereon, and a sealing plate bonded thereto, the electrode wirings are made of wiring metal containing gold (Au) on the drive substrate through an adhesion layer which is a base layer, and has a removed portion in which a portion of the wiring metal in a region containing a part bonded to a bonding resin is removed and the adhesion layer is exposed.

Highly reliable chip mounting is accomplished by using a substrate having such a shape that a stress exerted on a flip-chip-connected chip can be reduced, so that the stress exerted on the chip is reduced and separation of an interlayer insulating layer having a low dielectric constant (low-k) is minimized. Specifically, in a chip mounting structure, a chip including an interlayer insulating layer having a low dielectric constant (low-k) is flip-chip connected to a substrate via bumps is shown. In the chip mounting structure, the substrate has such a shape that a mechanical stress exerted on the interlayer insulating layer at corner portions of the chip due to a thermal stress is reduced, the thermal stress occurring due to a difference in coefficient of thermal expansion between the chip and the substrate.

A substrate treating apparatus for treating substrates includes a plurality of substrate treatment lines arranged vertically for carrying out plural types of treatment on the substrates while transporting the substrates substantially horizontally, and a controller for changing processes of treatment carried out on the substrates for each of the substrate treatment lines. By changing the processes of treatment carried out for the substrates for each substrate treatment line, the processes of treatment carried out for the substrates can be changed for each substrate conveniently. Thus, a plurality of different processes of treatment corresponding to the number of substrate treatment lines can be carried out in parallel for the respective substrates.

The present invention discloses a three-dimensional chip stacking structure and preparing method, the method comprises: preparing a semi-cured organic film at a first surface and/or a second surface of a chip, and opening a window on the semi-cured organic film to expose the first conductive structure and/or the second conductive structure; completing a multi-layer chip stack by sequentially fixing the first conductive structure of an upper-layer chip to prickles of the second conductive structure of a lower-layer chip at a lower temperature; applying pressure to a top portion of the stacked multi-layer chip, and immersing a side wall of the metal bump and the prickles of the second conductive structure of the lower-layer chip in the first conductive structure of the upper-layer chip of the stacked multi-layer chip by means of a vacuum reflow process; heating the organic film to fully cure the organic film.