Patent classifications
H01L2224/27848
BONDED BODY AND METHOD FOR MANUFACTURING SAME
A bonded body is provided including: a bonding layer containing Cu; and a semiconductor element bonded to the bonding layer. The bonding layer includes an extending portion laterally extending from a peripheral edge of the semiconductor element. In a cross-sectional view in a thickness direction, the extending portion rises from a peripheral edge of a bottom of the semiconductor element or from the vicinity of the peripheral edge of the bottom of the semiconductor element, and includes a side wall substantially spaced apart from a side of the semiconductor element. Preferably, the extending portion does not include any portion where the side wall and the side of the semiconductor element are in contact with each other. A method for manufacturing a bonded body is also provided.
SELECTIVELY BONDING LIGHT-EMITTING DEVICES VIA A PULSED LASER
The invention is directed towards enhanced systems and methods for employing a pulsed photon (or EM energy) source, such as but not limited to a laser, to electrically couple, bond, and/or affix the electrical contacts of a semiconductor device to the electrical contacts of another semiconductor devices. Full or partial rows of LEDs are electrically coupled, bonded, and/or affixed to a backplane of a display device. The LEDs may be μLEDs. The pulsed photon source is employed to irradiate the LEDs with scanning photon pulses. The EM radiation is absorbed by either the surfaces, bulk, substrate, the electrical contacts of the LED, and/or electrical contacts of the backplane to generate thermal energy that induces the bonding between the electrical contacts of the LEDs' electrical contacts and backplane's electrical contacts. The temporal and spatial profiles of the photon pulses, as well as a pulsing frequency and a scanning frequency of the photon source, are selected to control for adverse thermal effects.
SELECTIVELY BONDING LIGHT-EMITTING DEVICES VIA A PULSED LASER
The invention is directed towards enhanced systems and methods for employing a pulsed photon (or EM energy) source, such as but not limited to a laser, to electrically couple, bond, and/or affix the electrical contacts of a semiconductor device to the electrical contacts of another semiconductor devices. Full or partial rows of LEDs are electrically coupled, bonded, and/or affixed to a backplane of a display device. The LEDs may be μLEDs. The pulsed photon source is employed to irradiate the LEDs with scanning photon pulses. The EM radiation is absorbed by either the surfaces, bulk, substrate, the electrical contacts of the LED, and/or electrical contacts of the backplane to generate thermal energy that induces the bonding between the electrical contacts of the LEDs' electrical contacts and backplane's electrical contacts. The temporal and spatial profiles of the photon pulses, as well as a pulsing frequency and a scanning frequency of the photon source, are selected to control for adverse thermal effects.
Semiconductor device
An object of the present invention is to provide a semiconductor device in which peeling between a mold resin and a substrate is suppressed. A semiconductor device 1 includes a semiconductor chip 20 and a substrate 10 that are molded with a mold resin layer 40. The semiconductor device 1 includes a resin layer 50 having a thickness of 200 nm or less different from the mold resin layer 40 between the cured mold resin layer 40 and the substrate 10. The resin layer 50 present between the mold resin layer 40 and the substrate 10 is preferably present on a periphery of 30% or more of the chip when an entire peripheral length of the chip is 100%.
Semiconductor device
An object of the present invention is to provide a semiconductor device in which peeling between a mold resin and a substrate is suppressed. A semiconductor device 1 includes a semiconductor chip 20 and a substrate 10 that are molded with a mold resin layer 40. The semiconductor device 1 includes a resin layer 50 having a thickness of 200 nm or less different from the mold resin layer 40 between the cured mold resin layer 40 and the substrate 10. The resin layer 50 present between the mold resin layer 40 and the substrate 10 is preferably present on a periphery of 30% or more of the chip when an entire peripheral length of the chip is 100%.
Electronic-component-mounted module design to reduce linear expansion coefficient mismatches
An electronic-component-mounted module has an electronic component, a first silver-sintered bonding layer bonded on one surface of the electronic component, a circuit layer made of copper or copper alloy and bonded on the first silver-sintered bonding layer, and a ceramic substrate board bonded on the circuit layer, and further has an insulation circuit substrate board with smaller linear expansion coefficient than the electronic component, a second silver-sintered bonding layer bonded on the other surface of the electronic component, and a lead frame with smaller linear expansion coefficient than the electronic component bonded on the second silver-sintered bonding layer; and a difference in the linear expansion coefficient between the insulation circuit substrate board and the lead frame is not more than 5 ppm/° C.
Electronic-component-mounted module design to reduce linear expansion coefficient mismatches
An electronic-component-mounted module has an electronic component, a first silver-sintered bonding layer bonded on one surface of the electronic component, a circuit layer made of copper or copper alloy and bonded on the first silver-sintered bonding layer, and a ceramic substrate board bonded on the circuit layer, and further has an insulation circuit substrate board with smaller linear expansion coefficient than the electronic component, a second silver-sintered bonding layer bonded on the other surface of the electronic component, and a lead frame with smaller linear expansion coefficient than the electronic component bonded on the second silver-sintered bonding layer; and a difference in the linear expansion coefficient between the insulation circuit substrate board and the lead frame is not more than 5 ppm/° C.
Manufacturing method for semiconductor apparatus and semiconductor apparatus
A manufacturing method for a semiconductor apparatus sequentially includes bonding a first chip and a second chip together using an adhesive. The first chip includes a first electrode and has a protrusion, and the second chip has a recess. In the bonding, the first chip and the second chip are bonded together in such a manner that the protrusion is positioned into the recess. Further, the method includes forming a through hole in the second chip to expose the first electrode, the first surface being opposite to a second surface having the recess, and forming the second electrode which is electrically connected to the first electrode, in the through hole.
METHOD FOR PRODUCING BONDED OBJECT AND SEMICONDUCTOR DEVICE AND COPPER BONDING PASTE
An embodiment of the present invention provides a method for producing a bonded object. The method comprises a step for preparing a laminate in which a first member, a copper bonding paste, and a second member are laminated in order and a step for sintering the copper bonding paste under a pressure of 0.1-1 MPa. The copper bonding paste contains metal particles and a dispersion medium, wherein the content of metal particles is at 50 mass % or more with respect to the total mass of the copper bonding paste, and the metal particles contain 95 mass % or more of submicro copper particles with respect to the total mass of the metal particles.
Semiconductor Device that Uses Bonding Layer to Join Semiconductor Substrates Together
Semiconductor devices are provided in which a first semiconductor device is bonded to a second semiconductor device. The bonding may occur at a gate level, a gate contact level, a first metallization layer, a middle metallization layer, or a top metallization layer of either the first semiconductor device or the second semiconductor device.