A printed circuit board includes: a first insulating layer; a first cavity disposed in one surface of the first insulating layer; a plurality of protrusion portions spaced apart from each other in the first cavity; and a first wiring layer embedded in the one surface of the first insulating layer.

According to the present disclosure, a semiconductor apparatus comprises an insulating substrate. A porous material is directly bonded to the insulating substrate. And a semiconductor device is bonded to the porous material via a bonding material. The bonding material contains metal nanoparticles.

A semiconductor device includes a power semiconductor device, a circuit board, and an insulating substrate. The power semiconductor device includes contact pads. Adjacent ones of the contact pads are separated by one of a plurality of gaps. The circuit board includes traces for coupling with the contact pads of the power semiconductor device. The contact pads are physically attached to the traces. The insulating substrate is disposed between the circuit board and the power semiconductor device, where portions of the insulating substrate are disposed in the plurality of gaps, and where the insulating substrate has a monolithic structure.

A semiconductor package includes a first package substrate, a first semiconductor chip on the first package substrate, a plurality of first chip connection units to connect the first package substrate to the first semiconductor chip, an interposer on the first semiconductor chip, the interposer having a width greater than a width of the first semiconductor chip in a direction parallel to an upper surface of the first package substrate, and an upper filling layer including a center portion and an outer portion, the center portion being between the first semiconductor chip and the interposer, and the outer portion surrounding the center portion and having a thickness greater than a thickness of the center portion in a direction perpendicular to the upper surface of the first package substrate.

A semiconductor package includes a first package substrate, a first semiconductor chip on the first package substrate, a plurality of first chip connection units to connect the first package substrate to the first semiconductor chip, an interposer on the first semiconductor chip, the interposer having a width greater than a width of the first semiconductor chip in a direction parallel to an upper surface of the first package substrate, and an upper filling layer including a center portion and an outer portion, the center portion being between the first semiconductor chip and the interposer, and the outer portion surrounding the center portion and having a thickness greater than a thickness of the center portion in a direction perpendicular to the upper surface of the first package substrate.

An electronic device includes a substrate, a first pad disposed on the substrate, a second pad disposed opposite to the first pad, and a conductive particle disposed between the first pad and the second pad. The first pad has a recess, and a part of the conductive particle sinks in the recess.

An electronic device includes a substrate, a first pad disposed on the substrate, a second pad disposed opposite to the first pad, and a conductive particle disposed between the first pad and the second pad. The first pad has a recess, and a part of the conductive particle sinks in the recess.

A semiconductor package includes a circuit board, an interposer structure on the circuit board, a first semiconductor chip and a second semiconductor chip on the interposer structure, the first and the second semiconductor chips electrically connected to the interposer structure and spaced apart from each other, and a mold layer between the first and second semiconductor chips, the mold layer separating the first and second semiconductor chips. A slope of a side wall of the mold layer is constant as the side wall extends away from an upper side of the interposer structure, and an angle defined by a bottom side of the mold layer and the side wall of the mold layer is less than or equal to ninety degrees.

A semiconductor device includes a heat dissipating component and a semiconductor module. The semiconductor module includes: a metal plate bonded to a bonded region on the upper surface of the heat dissipating component via a bonding material; an insulating layer disposed on an upper surface of the metal plate; a metal component disposed on an upper surface of the insulating layer; a semiconductor element disposed on an upper surface of the metal component; and a sealant sealing the metal plate, the insulating layer, the metal component, and the semiconductor element with a lower surface of the metal plate being exposed. The heat dissipating component includes a step formed around an outer periphery of the bonded region so that the outer periphery is lower than the bonded region, and a resin for protecting a bonded portion between the semiconductor module and the heat dissipating component is applied to the step.

A semiconductor package may include: a substrate having a first side and a second side on a same plane; a first semiconductor chip disposed over the second side of the substrate; a first one-side third semiconductor chip stack disposed over the first side of the substrate and spaced apart from the first semiconductor chip; a second semiconductor chip stack disposed over the first semiconductor chip and the first one-side third semiconductor chip stack, the second semiconductor chip stack including one or more second semiconductor chips; and a second one-side third semiconductor chip stack disposed over the second semiconductor chip stack, wherein each of the third semiconductor chip stacks includes a plurality of third semiconductor chips that are offset-stacked, offset towards the first side as the third semiconductor chips are farther from the substrate, each of the third semiconductor chip stacks being electrically connected to the substrate.