Patent classifications
H01L2224/321
DIE WITH METAL PILLARS
The present disclosure relates to a die comprising metal pillars extending from a surface of the die, the height of each pillar being substantially equal to or greater than 20 m, the pillars being intended to raise the die when fastening the die by means of a bonding material on a surface of a support. The metal pillars being inserted into the bonding material at which point the bonding material is annealed to be cured and hardened solidifying the bonding material to couple the die to the surface of the support.
LASER ABLATION-BASED SURFACE PROPERTY MODIFICATION AND CONTAMINATION REMOVAL
Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a mold layer and a die embedded in the mold layer. In an embodiment the electronic package further comprises a solder resist with a first surface over the mold layer and a second surface opposite from the first surface. In an embodiment, the second surface comprises a first cavity into the solder resist.
LASER ABLATION-BASED SURFACE PROPERTY MODIFICATION AND CONTAMINATION REMOVAL
Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a mold layer and a die embedded in the mold layer. In an embodiment the electronic package further comprises a solder resist with a first surface over the mold layer and a second surface opposite from the first surface. In an embodiment, the second surface comprises a first cavity into the solder resist.
Semiconductor light emitting element with magnetic layer, manufacturing method thereof, and display device including the same
A semiconductor light emitting element can include an n-type semiconductor layer, a p-type semiconductor layer in a first region on the n-type semiconductor layer, a p-type electrode on the p-type semiconductor layer, an n-type electrode in a second region different from the first region on the n-type semiconductor layer, a magnetic layer under the n-type semiconductor layer, a reflective layer between the n-type semiconductor layer and the magnetic layer, and a passivation layer surrounding the n-type semiconductor layer, the p-type semiconductor layer, the p-type electrode, the n-type electrode, and the magnetic layer.
SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
The present disclosure provides a semiconductor structure including a substrate, a first die over the substrate, a second die over the first die, a heat spreader having a sidewall facing toward and proximal to a sidewall of the first die, and a thermal interface material (TIM) between the sidewall of the first die and the sidewall of the heat spreader. A thermal conductivity of the heat spreader is higher than a thermal conductivity of the TIM.
METHOD FOR PRODUCING MEMBER FOR SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE, AND MEMBER FOR SEMICONDUCTOR DEVICE
A member for semiconductor device includes a metal portion configured to be bonded to another member by solder, and a treated coating covering a surface of the metal portion, the treated coating including a treatment agent. The treated coating vaporizes at a temperature lower than or equal to a solidus temperature of the solder.
Method for producing member for semiconductor device and semiconductor device, and member for semiconductor device
There is provided a method for producing a member for semiconductor device which can reduce generation of a large number of voids in a solder-bonded portion without increasing production cost. The method includes the step of preparing a first member including a metal portion capable of being bonded by solder and the step of coating the surface of the metal portion of the first member with a treatment agent to form a treated coating which vaporizes at a temperature lower than or equal to the solidus temperature of the solder.
Controlling of height of high-density interconnection structure on substrate
An interconnection layer carrying structure for transferring an interconnection layer onto a substrate is disclosed. The interconnection layer carrying structure includes a support substrate, a release layer on the support substrate; and an interconnection layer on the release layer. The interconnection layer includes an organic insulating material and a set of pads embedded in the organic insulating material. The set of the pads is configured to face towards the support substrate. The support substrate has a base part where the interconnection layer is formed and an extended part extending outside the base part.
Controlling of height of high-density interconnection structure on substrate
An interconnection layer carrying structure for transferring an interconnection layer onto a substrate is disclosed. The interconnection layer carrying structure includes a support substrate, a release layer on the support substrate; and an interconnection layer on the release layer. The interconnection layer includes an organic insulating material and a set of pads embedded in the organic insulating material. The set of the pads is configured to face towards the support substrate. The support substrate has a base part where the interconnection layer is formed and an extended part extending outside the base part.
METHOD FOR PRODUCING MEMBER FOR SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE, AND MEMBER FOR SEMICONDUCTOR DEVICE
There is provided a method for producing a member for semiconductor device which can reduce generation of a large number of voids in a solder-bonded portion without increasing production cost. The method includes the step of preparing a first member including a metal portion capable of being bonded by solder and the step of coating the surface of the metal portion of the first member with a treatment agent to form a treated coating which vaporizes at a temperature lower than or equal to the solidus temperature of the solder.