The present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a substrate, a die and a first adhesive layer; a surface of the substrate is provided with an insulation layer; the die is arranged on a surface of the insulation layer via the first adhesive layer; the insulation layer is provided with at least one slot; a position of the at least one slot corresponds to at least a part of an edge of the first adhesive layer; a second adhesive layer is arranged in the at least one slot; at least a part of a surface of the second adhesive layer is connected with the first adhesive layer; and an elasticity modulus of the second adhesive layer is smaller than an elasticity modulus of the first adhesive layer.

The present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a substrate, a die and a first adhesive layer; a surface of the substrate is provided with an insulation layer; the die is arranged on a surface of the insulation layer via the first adhesive layer; the insulation layer is provided with at least one slot; a position of the at least one slot corresponds to at least a part of an edge of the first adhesive layer; a second adhesive layer is arranged in the at least one slot; at least a part of a surface of the second adhesive layer is connected with the first adhesive layer; and an elasticity modulus of the second adhesive layer is smaller than an elasticity modulus of the first adhesive layer.

The present disclosure relates to a fabrication process of a semiconductor chip, which starts with providing a precursor wafer mounted on a carrier. The precursor wafer includes a precursor substrate and component portions between the carrier and the precursor substrate. The precursor substrate is then thinned down to provide a thinned substrate, which includes a substrate base adjacent to the component portions and an etchable region over the substrate base. Next, the etchable region is selectively etched to generate a number of protrusions over the substrate base. Herein, the substrate base is retained, and portions of the substrate base are exposed through the protrusions. Each protrusion protrudes from the substrate base and has a same height. A metal layer is then applied to provide a semiconductor wafer. The metal layer selectively covers the exposed portions of the substrate base and covers at least a portion of each protrusion.

The present disclosure relates to a fabrication process of a semiconductor chip, which starts with providing a precursor wafer mounted on a carrier. The precursor wafer includes a precursor substrate and component portions between the carrier and the precursor substrate. The precursor substrate is then thinned down to provide a thinned substrate, which includes a substrate base adjacent to the component portions and an etchable region over the substrate base. Next, the etchable region is selectively etched to generate a number of protrusions over the substrate base. Herein, the substrate base is retained, and portions of the substrate base are exposed through the protrusions. Each protrusion protrudes from the substrate base and has a same height. A metal layer is then applied to provide a semiconductor wafer. The metal layer selectively covers the exposed portions of the substrate base and covers at least a portion of each protrusion.

A method of batch soldering includes: forming a soldered joint between a metal region of a first semiconductor die and a metal region of a substrate using a solder preform via a soldering process which does not apply pressure directly to the first semiconductor die, the solder preform having a maximum thickness of 30 μm and a lower melting point than the metal regions; setting a soldering temperature of the soldering process so that the solder preform melts and fully reacts with the metal region of the first semiconductor die and the metal region of the substrate to form one or more intermetallic phases throughout the entire soldered joint, each intermetallic phase having a melting point above the preform melting point and the soldering temperature; and soldering a second semiconductor die to the same or different metal region of the substrate, without applying pressure directly to the second semiconductor die.

A method of batch soldering includes: forming a soldered joint between a metal region of a first semiconductor die and a metal region of a substrate using a solder preform via a soldering process which does not apply pressure directly to the first semiconductor die, the solder preform having a maximum thickness of 30 μm and a lower melting point than the metal regions; setting a soldering temperature of the soldering process so that the solder preform melts and fully reacts with the metal region of the first semiconductor die and the metal region of the substrate to form one or more intermetallic phases throughout the entire soldered joint, each intermetallic phase having a melting point above the preform melting point and the soldering temperature; and soldering a second semiconductor die to the same or different metal region of the substrate, without applying pressure directly to the second semiconductor die.

The present disclosure relates to a semiconductor chip that includes a substrate, a metal layer, and a number of component portions. Herein, the substrate has a substrate base and a number of protrusions protruding from a bottom surface of the substrate base. The substrate base and the protrusions are formed of a same material. Each of the protrusions has a same height. At least one via hole extends vertically through one protrusion and the substrate base. The metal layer selectively covers exposed surfaces at a backside of the substrate and fully covers inner surfaces of the at least one via hole. The component portions reside over a top surface of the substrate base, such that a certain one of the component portions is electrically coupled to a portion of the metal layer at the top of the at least one via hole.

The present disclosure relates to a semiconductor chip that includes a substrate, a metal layer, and a number of component portions. Herein, the substrate has a substrate base and a number of protrusions protruding from a bottom surface of the substrate base. The substrate base and the protrusions are formed of a same material. Each of the protrusions has a same height. At least one via hole extends vertically through one protrusion and the substrate base. The metal layer selectively covers exposed surfaces at a backside of the substrate and fully covers inner surfaces of the at least one via hole. The component portions reside over a top surface of the substrate base, such that a certain one of the component portions is electrically coupled to a portion of the metal layer at the top of the at least one via hole.

A method of batch soldering includes: forming a soldered joint between a metal region of a first semiconductor die and a metal region of a substrate using a solder preform via a soldering process which does not apply pressure directly to the first semiconductor die, the solder preform having a maximum thickness of 30 μm and a lower melting point than the metal regions; setting a soldering temperature of the soldering process so that the solder preform melts and fully reacts with the metal region of the first semiconductor die and the metal region of the substrate to form one or more intermetallic phases throughout the entire soldered joint, each intermetallic phase having a melting point above the preform melting point and the soldering temperature; and soldering a second semiconductor die to the same or different metal region of the substrate, without applying pressure directly to the second semiconductor die.

A method of batch soldering includes: forming a soldered joint between a metal region of a first semiconductor die and a metal region of a substrate using a solder preform via a soldering process which does not apply pressure directly to the first semiconductor die, the solder preform having a maximum thickness of 30 μm and a lower melting point than the metal regions; setting a soldering temperature of the soldering process so that the solder preform melts and fully reacts with the metal region of the first semiconductor die and the metal region of the substrate to form one or more intermetallic phases throughout the entire soldered joint, each intermetallic phase having a melting point above the preform melting point and the soldering temperature; and soldering a second semiconductor die to the same or different metal region of the substrate, without applying pressure directly to the second semiconductor die.