Patent classifications
H01L2224/4005
ELECTRONIC MODULE, METHOD OF MANUFACTURING CONNECTOR, AND METHOD OF MANUFACTURING ELECTRONIC MODULE
An electronic module has a first electronic element 13, a first connector 60 provided in one side of the first electronic element 13, and having a first columnar part 62 extending to another side and a first groove part 64 provided in a one-side surface, and a second electronic element 23 provided in one side of the first connector 60 via a conductive adhesive agent provided inside a circumference of the first groove part 64. The first connector 60 has a first concave part 67 on one side at a position corresponding to the first columnar part 62.
ELECTRONIC MODULE, METHOD OF MANUFACTURING CONNECTOR, AND METHOD OF MANUFACTURING ELECTRONIC MODULE
An electronic module has a first electronic element 13, a first connector 60 provided in one side of the first electronic element 13, and having a first columnar part 62 extending to another side and a first groove part 64 provided in a one-side surface, and a second electronic element 23 provided in one side of the first connector 60 via a conductive adhesive agent provided inside a circumference of the first groove part 64. The first connector 60 has a first concave part 67 on one side at a position corresponding to the first columnar part 62.
SEMICONDUCTOR CHIP PACKAGE COMPRISING SUBSTRATE, SEMICONDUCTOR CHIP, AND LEADFRAME AND A METHOD FOR FABRICATING THE SAME
A semiconductor chip package is provided with improved connections between different components within the package. The semiconductor chip package may comprise a semiconductor chip disposed on a substrate. The semiconductor chip may have a first surface and a second surface. The first surface of the semiconductor chip may be connected to the substrate. The semiconductor chip package may comprise a leadframe that includes a first lead and a second lead. The first lead of the leadframe may be directly attached to the second surface of the semiconductor chip. The second lead of the leadframe may be directly attached to the substrate.
SEMICONDUCTOR CHIP PACKAGE COMPRISING SUBSTRATE, SEMICONDUCTOR CHIP, AND LEADFRAME AND A METHOD FOR FABRICATING THE SAME
A semiconductor chip package is provided with improved connections between different components within the package. The semiconductor chip package may comprise a semiconductor chip disposed on a substrate. The semiconductor chip may have a first surface and a second surface. The first surface of the semiconductor chip may be connected to the substrate. The semiconductor chip package may comprise a leadframe that includes a first lead and a second lead. The first lead of the leadframe may be directly attached to the second surface of the semiconductor chip. The second lead of the leadframe may be directly attached to the substrate.
Electrode terminal, semiconductor device, and power conversion apparatus
An electrode terminal includes a body and a first bonding part. The body includes a first metal material. Then, the first bonding part is bonded to one end of the body, and includes a second metal material which is a clad material other than the first metal material. The first bonding part is ultrasonically bondable to a first bonded member. An elastic part which is elastically deformable is provided between the one end of the body and the other end of the body.
Semiconductor module with temperature detecting element
In a semiconductor module, first and second semiconductor chips each include a transistor and a temperature-detecting diode connected between first and second control pads. The first control pad of the first semiconductor chip is connected to a first control terminal, the second control pad of the first semiconductor chip and the first control pad of the second semiconductor chip are connected to a second control terminal, and the second control pad of the second semiconductor chip is connected to a third control terminal.
Patterned die pad for packaged vertical semiconductor devices
A method of semiconductor device packaging to form a packaged semiconductor device includes providing (i) a vertical power semiconductor device die including a semiconductor substrate including a control node, a source or emitter on a top side or on a bottom side of the substrate, and a drain or a collector on another of the top side the bottom side, a backside metal (BSM) layer on the bottom side, and (ii) a leadframe. The leadframe includes a patterned die pad that includes a common continuous base portion and a two-dimensional array of spaced apart posts extending up from the base portion, with a separate solder cap on a top of the posts. The BSM layer is placed on the solder caps, and reflow processing bonds the BSM layer to the solder caps.
PATTERNED DIE PAD FOR PACKAGED VERTICAL SEMICONDUCTOR DEVICES
A method of semiconductor device packaging to form a packaged semiconductor device includes providing (i) a vertical power semiconductor device die including a semiconductor substrate including a control node, a source or emitter on a top side or on a bottom side of the substrate, and a drain or a collector on another of the top side the bottom side, a backside metal (BSM) layer on the bottom side, and (ii) a leadframe. The leadframe includes a patterned die pad that includes a common continuous base portion and a two-dimensional array of spaced apart posts extending up from the base portion, with a separate solder cap on a top of the posts. The BSM layer is placed on the solder caps, and reflow processing bonds the BSM layer to the solder caps.
LONG-LIFE EXTENDED TEMPERATURE RANGE EMBEDDED DIODE DESIGN FOR ELECTROSTATIC CHUCK WITH MULTIPLEXED HEATERS ARRAY
A substrate support for a plasma chamber includes a base plate arranged along a plane, a first layer of an electrically insulating material arranged on the base plate along the plane, a plurality of heating elements arranged in the first layer along the plane, and a plurality of diodes arranged in respective cavities in the first layer. The plurality of diodes are connected in series to the plurality of heating elements, respectively. Each of the plurality of diodes includes a die of a semiconductor material arranged in a respective one of the cavities. The semiconductor material has a first coefficient of thermal expansion. A first side of the die is arranged on the first layer along the plane. A first terminal of the die is connected to a first electrical contact on the first layer.
POWER ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME
A power electronic device includes: a carrier having at least two die mounting areas; a power semiconductor die(s) mounted on the carrier at a first mounting area and having a first side facing the carrier and an opposite second side, a second die mounting area being free of any semiconductor die; and a contact clip arranged over the die and second die mounting area. The contact clip is at least partially arranged in a first plane, with a first part over the die being bent downwards such it is arranged in a second plane below the first plane and coupled to the second side of the die. A second part of the contact clip over the second die mounting area is bent upwards such that the second part is arranged in a third plane above the first plane, or is free of any bend and arranged in the first plane.