A semiconductor device includes a first semiconductor chip that includes a first conductive pad whose top surface is exposed; and a second semiconductor chip that includes a second conductive pad whose top surface is exposed and in contact with at least a portion of the top surface of the first conductive pad. The first semiconductor chip may include a first diffusion barrier in contact with a bottom surface of the first conductive pad, and a second diffusion barrier in contact with a lateral surface of the first conductive pad, and the first diffusion barrier and the second diffusion barrier may include different materials from each other.

A semiconductor chip including a semiconductor substrate having a first surface and a second surface and having an active layer in a region adjacent to the first surface, a first through electrode penetrating at least a portion of the semiconductor substrate and connected to the active layer, a second through electrode located at a greater radial location from the center of the semiconductor substrate than the first through electrode, penetrating at least a portion of the semiconductor substrate, and connected to the active layer. The semiconductor chip also including a first chip connection pad having a first height and a first width, located on the second surface of the semiconductor substrate, and connected to the first through electrode, and a second chip connection pad having a second height greater than the first height and a second width greater than the first width, located on the second surface of the semiconductor substrate, and connected to the second through electrode.

An electronic component mounting device (100) bonds a semiconductor die (150) to a substrate by thermocompression bonding, and seals, using an insulating resin, a gap between the semiconductor die (150) and the substrate. The electronic component mounting device is provided with: a film cutting mechanism (200) for cutting a long film (210) into cut pieces; and a mounting tool (110), which vacuum-sucks the semiconductor die (150), and bonds the die to the substrate by thermocompression bonding. Consequently, in the electronic component mounting device (100) that moves a mounting head in the horizontal direction, adhesion of the insulating resin to the mounting tool can be suppressed.

The invention is directed towards enhanced systems and methods for employing a pulsed photon (or EM energy) source, such as but not limited to a laser, to electrically couple, bond, and/or affix the electrical contacts of a semiconductor device to the electrical contacts of another semiconductor devices. Full or partial rows of LEDs are electrically coupled, bonded, and/or affixed to a backplane of a display device. The LEDs may be μLEDs. The pulsed photon source is employed to irradiate the LEDs with scanning photon pulses. The EM radiation is absorbed by either the surfaces, bulk, substrate, the electrical contacts of the LED, and/or electrical contacts of the backplane to generate thermal energy that induces the bonding between the electrical contacts of the LEDs' electrical contacts and backplane's electrical contacts. The temporal and spatial profiles of the photon pulses, as well as a pulsing frequency and a scanning frequency of the photon source, are selected to control for adverse thermal effects.

A semiconductor package including a first die, through electrodes penetrating the first die, a first pad on a top surface of the first die and coupled to a through electrode, a second die on the first die, a second pad on a bottom surface of the second die, a first connection terminal connecting the first pad to the second pad, and an insulating layer that fills a region between the first die and the second die and encloses the first connection terminal. The first connection terminal includes an intermetallic compound made of solder material and metallic material of the first and second pads. A concentration of the metallic material in the first connection terminal is substantially constant regardless of a distance from the first pad or the second pad.

Semiconductor device packages may include a bottom-most semiconductor die, at least one intermediate semiconductor die stacked over the bottom-most semiconductor die, and a top-most semiconductor die located on a side of a farthest intermediate semiconductor die from the bottom-most semiconductor die opposite the bottom-most semiconductor die. The bottom-most semiconductor die and each intermediate semiconductor die may include vias extending therethrough. The bottom-most semiconductor die may have a larger foot print than each intermediate semiconductor die and the top-most semiconductor die. A dielectric material may be located between each of the semiconductor dice, at least sections of the dielectric material extending contiguously from between adjacent semiconductor dice, over sidewalls thereof, and laterally beyond the lateral peripheries all but the bottom-most semiconductor die

A device comprising a connecting plate and a circuit element is disclosed. The circuit element is electrically coupled to the connecting plate through a solder connection including a plurality of solder balls disposed between the circuit element and the connecting plate. An underfill layer is formed between the circuit element and the connecting plate and configured to provide bonding between the circuit element and the connecting plate. The solder connection includes a first solder area with a first solder ball density and a second solder area with a second solder ball density. The first solder ball density is less than the second solder ball density. The underfill layer includes a bonding material continuously disposed in the second solder area of the solder connection.

Disclosed is a microelectronic device assembly comprising a substrate having conductors exposed on a surface thereof. Two or more stacks of microelectronic devices are located on the substrate, and microelectronic devices of the stacks are connected to vertical conductive paths external to the stacks and extending to the substrate and to lateral conductive paths extending between the stacks. Methods of fabrication are also disclosed.

According to an aspect of the inventive concept, there is provided a die-to-wafer bonding structure including a die having a first test pad, a first bonding pad formed on the first test pad, and a first insulating layer, the first bonding pad penetrates the first insulating layer. The structure may further include a wafer having a second test pad, a second bonding pad formed on the second test pad, and a second insulating layer, the second bonding pad penetrates the second insulating layer. The structure may further include a polymer layer surrounding all side surfaces of the first bonding pad and all side surfaces of the second bonding pad, the polymer layer being arranged between the die and the wafer. Additionally, the wafer and the die may be bonded together.

A semiconductor device includes a semiconductor die having an active surface, an opposite surface, a vertical sidewall extending between the active surface and the opposite surface, and input/output (I/O) connections disposed on the active surface. A redistribution layer (RDL) is disposed on the active surface of the semiconductor die. A plurality of first connecting elements is disposed on the RDL. A molding compound encapsulates the opposite surface and the vertical sidewall of the semiconductor die. The molding compound also covers the RDL and surrounds the plurality of first connecting elements. An interconnect substrate is mounted on the plurality of first connecting elements and on the molding compound.