A semiconductor device including a first die and a second die bonded to one another. The first die includes a first passivation layer over a substrate, and first bond pads in the first passivation layer. The second die includes a second passivation layer, which may be bonded to the first passivation layer, and second bond pads in the second passivation layer, which may be bonded to the first bond pads. The second bond pads include inner bond pads and outer bond pads. The outer bond pads may have a greater diameter than the inner bond pads as well as the first bond pads.

In a wafer to wafer bonding method, a first wafer is vacuum suctions on a first surface of a lower stage and a second wafer is vacuum suctioned on a second surface of an upper stage. Pressure is applied to a middle portion of the first wafer by a lower push rod and pressure is applied to a middle portion of the second wafer by an upper push rod. Bonding of the first and second wafers propagates radially outwards. A bonding propagation position of the first and second wafers is detected. A ratio of protruding lengths of the lower push rod and the upper push rod is changed according to the bonding propagation position.

A 3D semiconductor device, the device including: a first die including first transistors and first interconnect; and a second die including second transistors and second interconnect, where the first die is overlaid by the second die, where the first die has a first die area and the second die has a second die area, where the first die area is at least 10% larger than the second die area, where the second die is pretested, where the second die includes an array of memory cells, where the first die includes control logic to control reads and writes to the array of memory cells, where the second die is bonded to the first die, and where the bonded includes hybrid bonding.

A bonding structure and a method for manufacturing the same. First edge trimming is performed from the bonding surface of an n-th wafer in bonding the n-th wafer and an (n1)th wafer, and a width of the first edge trimming is W.sub.n. As n increases, the width of the first edge trimming is gradually increased. In the trimming, a portion that is not even at the edge of the n-th wafer can be removed. The bonding surface of the n-th wafer faces the bonding surface of the (n1)-th wafer, so as to bond the n-th wafer and the (n1)-th wafer. Afterwards the substrate of the n-th wafer is thinned, so as to form the (n1)-th wafer stack. There is a reduced possibility that a gap exists between the bonding interfaces of the wafers, a bonding strength between the wafers is improved, and a risk of cracking is reduced.

A method is provided and includes the following steps. A first wafer is coupled to a first support of a bonding tool and a second wafer is coupled to a second support of the bonding tool. The second wafer is bonded to the first wafer with the first wafer coupled to the first support. Whether a bubble is between the bonded first and second wafers in the bonding tool is detected.

An alignment method for aligning two substrates to be stacked, comprising measuring a position of a mark selected from plurality of marks disposed on at least one substrate of the two substrates and aligning the two substrates based on the position of the measured mark, wherein the mark to be measured is selected based on information relating to distortion of the at least one substrate. The mark may be a mark disposed in a region having a smaller distortion amount of the at least one substrate than a threshold. The mark may be a mark disposed in a region having a higher reproducibility of distortion that occurs in the at least one substrate than a threshold.

A bonding system includes a substrate transfer device configured to transfer a first substrate and a second substrate to a bonding apparatus, a first holding plate configured to hold the first substrate from an upper surface side, and a second holding plate disposed below the first holding plate and configured to hold the second substrate from a lower surface side so that the second substrate faces the first substrate. The substrate transfer device includes a first holding part capable of holding the first substrate from the upper surface side, and a second holding part disposed below the first holding part and capable of holding the second substrate from the lower surface side. The first holding part and the second holding part are configured to receive and hold the first substrate and the second substrate at the same time from the first holding plate and the second holding plate.

A method of manufacturing a semiconductor memory device includes processing a first substrate including a first align mark and a first structure, processing a second substrate including a second align mark and a second structure, orientating the first substrate and the second substrate such that the first structure and the second structure face each other, and controlling alignment between the first structure and the second structure by using the first align mark and the second align mark to couple the first structure with the second structure.

A semiconductor wafer, a bonding structure, and a wafer bonding method are provided. In the semiconductor wafer, a bonding pad which is electrically connected to the interconnection structure is formed in the top cover layer, and a bonding alignment mark formed by a point array is disposed in the top cover layer. In this way, the bonding alignment mark is disposed in the top cover layer, and the top cover layer is not covered by another material layer, thereby facilitating recognition of the alignment pattern by the bonding device and increasing the alignment window in bonding process. Moreover, the bonding alignment mark is formed by a point array, thereby facilitating integration of the process for forming the bonding alignment mark with the bonding hole process and avoiding defects such as the dishing phenomenon in the manufacturing process.

A method to form a 3D semiconductor device, the method including: providing a first wafer including first circuits including transistors and interconnection; preparing a second wafer including a silicon layer; performing growth of an epitaxial layer on top of the silicon layer, the epitaxial layer including non-silicon atoms, forming second circuits over the second wafer, the second circuits including transistors and interconnection; transferring and then bonding the second wafer on top of the first wafer; and then thinning the second wafer to a thickness of less than ten microns.