A chip-placing method for performing an image alignment of chip placement comprises a chip pick-up step, a reference-image capturing step, an alignment-image capturing step, a calculating and processing step, a calibration adjusting step and a placing step. An image(s) of a marking member and a chip sucked by a chip-placing member is/are captured from an opposite direction so as to obtain a relative position information of the chip in relation to the marking member. An image showing the marking member and the substrate is captured from a backside so as to obtain a relative position information of the marking member in relation to the substrate. A position calibration relationship information of the position of the chip in relation to a to-be-placed location of the substrate is obtained according to those relative position information. Therefore, a relative position of the chip-placing member in relation to the to-be-placed location is calibrated.

Die stacks and methods of making die stacks with very thin dies are disclosed. The die surfaces remain flat within a 5 micron tolerance despite the thinness of the die and the process steps of making the die stack. A residual flux height is kept below 50% of the spacing distance between adjacent surfaces or structures, e.g. in the inter-die spacing.

Die stacks and methods of making die stacks with very thin dies are disclosed. The die surfaces remain flat within a 5 micron tolerance despite the thinness of the die and the process steps of making the die stack. A residual flux height is kept below 50% of the spacing distance between adjacent surfaces or structures, e.g. in the inter-die spacing.

Provided are a chip bonding apparatus and bonding method. The apparatus comprises: a chip supply unit (10); a substrate supply unit (20); a first pick-up assembly (30) arranged between the chip supply unit (10) and the substrate supply unit (20), comprising a first rotating component and a first pick-up head arranged on the first rotating component; a second pick-up assembly (40) comprising a second rotating component and a second pick-up head arranged on the second rotating component, wherein the first pick-up assembly (30) picks up a chip (60) from the chip supply unit (10) or the second pick-up assembly (40), and delivers the chip (60) onto a substrate of the substrate supply unit (20) to complete the bonding; and a vision unit (50) for realizing the alignment of the chip (60) and the substrate on the first pick-up assembly (30), wherein the chip supply unit (10), the substrate supply unit (20), the second pick-up assembly (40) and the vision unit (50) are respectively located on four work positions of the first pick-up head. The chip (60) is transported through rotation, improving the productivity of chip (60) bonding; and the chip (60) is reversed by utilizing the second pick-up assembly (40), which is compatible with two ways of bonding, i.e. a mark face of the chip (60) facing upwards and downwards.

Provided are a chip bonding apparatus and bonding method. The apparatus comprises: a chip supply unit (10); a substrate supply unit (20); a first pick-up assembly (30) arranged between the chip supply unit (10) and the substrate supply unit (20), comprising a first rotating component and a first pick-up head arranged on the first rotating component; a second pick-up assembly (40) comprising a second rotating component and a second pick-up head arranged on the second rotating component, wherein the first pick-up assembly (30) picks up a chip (60) from the chip supply unit (10) or the second pick-up assembly (40), and delivers the chip (60) onto a substrate of the substrate supply unit (20) to complete the bonding; and a vision unit (50) for realizing the alignment of the chip (60) and the substrate on the first pick-up assembly (30), wherein the chip supply unit (10), the substrate supply unit (20), the second pick-up assembly (40) and the vision unit (50) are respectively located on four work positions of the first pick-up head. The chip (60) is transported through rotation, improving the productivity of chip (60) bonding; and the chip (60) is reversed by utilizing the second pick-up assembly (40), which is compatible with two ways of bonding, i.e. a mark face of the chip (60) facing upwards and downwards.

A photodetector-array and fabrication method thereof are disclosed. The photodetector-array includes a first and second semiconductor structures having respective active regions defining respective pluralities of active photodetectors and active readout integrated circuit pixels (RICPs) electronically connectable to one another respectively. The first and second semiconductor structures are made with different semiconductor materials/compositions having different first and second coefficients of thermal expansion (CTEs) respectively. The pitch distances of the active photodetectors and the pitch distances of the respective active RICPs are configured in accordance with the difference between the first and second CTEs, such that at high temperatures, at which electrical coupling between the first and second semiconductor structures is performed, the electric contacts of the active photodetectors and of their respective RICPs overlap. Accordingly, after the first and second semiconductor structures are bonded together, at least 99.5% of the active photodetector are electrically connected with their respective RICPs.

The invention concerns the calibration of a component mounting apparatus configured to mount components on a substrate whose mounting places do not contain local markings. The substrate contains either global substrate markings attached to its edge or other global features that can be used to mount the components. Calibration is carried out by means of a calibration plate which has several calibration positions distributed two-dimensionally over the calibration plate and provided with first optical markings, a test chip which has second optical markings, and a holder attached to the bonding station for temporarily accommodating the calibration plate. The number and arrangement of the calibration positions of the calibration plate and the number and arrangement of the mounting places of the substrate areapart from possible exceptionsdifferent from one another.

A method for bonding two superconducting integrated circuits (chips), such that the bonds electrically interconnect the chips. A plurality of indium-coated metallic posts may be deposited on each chip. The indium bumps are aligned and compressed with moderate pressure at a temperature at which the indium is deformable but not molten, forming fully superconducting connections between the two chips when the indium is cooled down to the superconducting state. An anti-diffusion layer may be applied below the indium bumps to block reaction with underlying layers. The method is scalable to a large number of small contacts on the wafer scale, and may be used to manufacture a multi-chip module comprising a plurality of chips on a common carrier. Superconducting classical and quantum computers and superconducting sensor arrays may be packaged.

A method for bonding two superconducting integrated circuits (chips), such that the bonds electrically interconnect the chips. A plurality of indium-coated metallic posts may be deposited on each chip. The indium bumps are aligned and compressed with moderate pressure at a temperature at which the indium is deformable but not molten, forming fully superconducting connections between the two chips when the indium is cooled down to the superconducting state. An anti-diffusion layer may be applied below the indium bumps to block reaction with underlying layers. The method is scalable to a large number of small contacts on the wafer scale, and may be used to manufacture a multi-chip module comprising a plurality of chips on a common carrier. Superconducting classical and quantum computers and superconducting sensor arrays may be packaged.

In a method of aligning wafers, a second wafer having at least one second alignment key may be arranged over a first wafer having at least one first alignment key. At least one alignment hole may be formed by passing through the second wafer to expose the second alignment key and the first alignment key. The first wafer and the second wafer may be aligned with each other using the first alignment key and the second alignment key exposed through the alignment hole. Thus, the first alignment key and the second alignment key exposed through the alignment hole may be positioned at a same vertical line to accurately align the first wafer with the second wafer.