Methods, systems, and apparatuses for preventing corrosion between dissimilar bonded metals. The method includes providing a wafer having a plurality of circuits, each of the plurality of circuits having a plurality of bond pads including a first metal; applying a coating onto at least the plurality of bond pads; etching a hole in the coating on each of the plurality of bond pads to provide an exposed portion of the plurality of bond pads; dicing the wafer to separate each of the plurality of circuits; die bonding each of the plurality of circuits to a respective packaging substrate; and performing a bonding process to bond a second, dissimilar metal to the exposed portion of each of the plurality of bond pads such that the second, dissimilar metal encloses the hole in the coating of each of the plurality of bond pads, thereby enclosing the exposed portion.

A submount for connecting a semiconductor device to an external circuit, the submount comprising: a planar substrate formed from an insulating material and having relatively narrow edge surfaces and first and second relatively large face surfaces; at least one recess formed along an edge surface; a layer of a conducting material formed on a surface of each of the at least one recess; a first plurality of soldering pads on the first face surface configured to make electrical contact with a semiconductor device; and electrically conducting connections each of which electrically connects a soldering pad in the first plurality of soldering pads to the layer of conducting material of a recess of the at least one recess.

A multilayer substrate includes a flexible element assembly including a principal surface, a first to an n-th external electrode disposed on the principal surface, and at least one first dummy conductor disposed inside the element assembly and being in a floating state. When the element assembly is viewed from a normal direction that is normal to the principal surface, a distance between an m-th external electrode and a nearest external electrode therefrom among the first to the n-th external electrodes is defined as a distance Dm, an average of distances D1 to Dn is defined as an average Dave, and when the element assembly is viewed from the normal direction, an area within a circle with a center on the m-th external electrode and with a radius of Dm is defined as an area Am. The first dummy conductor is located in at least one area Am with a radius of Dm smaller than the average Dave when viewed from the normal direction.

A multilayer substrate includes a flexible element assembly including a principal surface, a first to an n-th external electrode disposed on the principal surface, and at least one first dummy conductor disposed inside the element assembly and being in a floating state. When the element assembly is viewed from a normal direction that is normal to the principal surface, a distance between an m-th external electrode and a nearest external electrode therefrom among the first to the n-th external electrodes is defined as a distance Dm, an average of distances D1 to Dn is defined as an average Dave, and when the element assembly is viewed from the normal direction, an area within a circle with a center on the m-th external electrode and with a radius of Dm is defined as an area Am. The first dummy conductor is located in at least one area Am with a radius of Dm smaller than the average Dave when viewed from the normal direction.

A jointed body that has been solid-phase jointed at normal temperature and that has a non-conventional structure is presented. The jointed body is formed by solid-phase joining a first jointed member to a second jointed member, and has a junction interface between the first member and the second member. This jointed body includes an average crystal grain size in a near interface structure that constitutes a near interface area having a total width of 20 micrometers and extending at both sides of the junction interface as a center is 75-100% of an average crystal grain size in an around interface structure that constitutes around interface areas located at both outer sides of the near interface area. In the jointed body, the near interface structure after the joining is almost the same as the structure before the joining, allowing the jointed body to exert similar characteristics to the jointed members.

An electronic component includes a substrate that has a first principal surface and a second principal surface, a chip that includes a mounting surface on which a plurality of terminal electrodes are formed and a non-mounting surface positioned on a side opposite to the mounting surface and that is arranged at the first principal surface of the substrate in a posture in which the mounting surface faces the first principal surface of the substrate, and a sealing resin that seals the chip at the first principal surface of the substrate so as to expose the non-mounting surface of the chip.

An electronic component includes a substrate that has a first principal surface and a second principal surface, a chip that includes a mounting surface on which a plurality of terminal electrodes are formed and a non-mounting surface positioned on a side opposite to the mounting surface and that is arranged at the first principal surface of the substrate in a posture in which the mounting surface faces the first principal surface of the substrate, and a sealing resin that seals the chip at the first principal surface of the substrate so as to expose the non-mounting surface of the chip.

A semiconductor chip 10 flip-chip mounted on a first surface 32 of a wiring substrate 30, a semiconductor chip 20 flip-chip mounted on a second surface 33 of the wiring substrate 30, a sealing resin 71 covering the semiconductor chip 10, a sealing resin 72 covering the semiconductor chip 20, a plurality of conductive posts provided to penetrate through the sealing resin 72, and a plurality of solder balls mounted on second ends of the plurality of conductive posts exposed from the sealing resin 72 are provided; and the mounting directions of the semiconductor chips 10 and 20 are mutually different by 90°. Both of the planar shapes of the semiconductor chips 10 and 20 are rectangular shapes, the semiconductor chip 10 is mounted so that the long sides thereof are parallel to the long sides of the wiring substrate 30, and the semiconductor chip 20 is mounted so that the long sides thereof are perpendicular to the long sides of the wiring substrate 30.

A semiconductor chip 10 flip-chip mounted on a first surface 32 of a wiring substrate 30, a semiconductor chip 20 flip-chip mounted on a second surface 33 of the wiring substrate 30, a sealing resin 71 covering the semiconductor chip 10, a sealing resin 72 covering the semiconductor chip 20, a plurality of conductive posts provided to penetrate through the sealing resin 72, and a plurality of solder balls mounted on second ends of the plurality of conductive posts exposed from the sealing resin 72 are provided; and the mounting directions of the semiconductor chips 10 and 20 are mutually different by 90°. Both of the planar shapes of the semiconductor chips 10 and 20 are rectangular shapes, the semiconductor chip 10 is mounted so that the long sides thereof are parallel to the long sides of the wiring substrate 30, and the semiconductor chip 20 is mounted so that the long sides thereof are perpendicular to the long sides of the wiring substrate 30.

A first insulating film is applied onto a joining face of a semiconductor device including a connection terminal on a joining face, and the connection terminal is embedded inside the first insulating film. The second insulating film is formed on a joining target face of a joining target, which includes a connection target terminal on the joining target face, and the connection target terminal is embedded inside the second insulating film. The semiconductor device and the joining target are joined together by applying pressure and causing the semiconductor device and the joining target to make contact with each other.