An integrated circuit is provided that comprises a first substrate having a plurality of conductive contact pads spaced apart from one another on a surface of the first substrate, a dielectric layer overlying the first substrate and the plurality of conductive contact pads, and a second substrate overlying the dielectric layer. A plurality of superconducting contacts extend through the second substrate and the dielectric layer to the first substrate, wherein each superconducting contact of the plurality of superconducting contacts is aligned with and in contact with a respective conductive contact pad of the plurality of conductive contact pads.

A memory device, a semiconductor device and their manufacturing methods are provided. One of the methods may include: providing a first die and a plurality of second dies, the first die having a first pad, each of the plurality of second dies having a second pad; stacking the plurality of second dies on the first die, the second pads and the first pad arranged in a stepwise manner, and projections of the second pads of any two adjacent second dies on the first die partially overlapped; forming a connecting hole passing through the second dies; and forming a conductive body filling the connecting hole and connecting the first pad and the second pads. This method simplifies the manufacturing process of a semiconductor device, reduces the cost thereof, and improves the production yield.

A wafer-level system-in-package (WLSiP) package structure is provided. The WLSiP package structure includes a device wafer, an adhesive layer, and a plurality of second chips. The device wafer includes a first front surface having a plurality of first chips integrated therein and a first back surface opposing the first front surface. The adhesive layer is formed on the first front surface of the device wafer and the adhesive layer includes a plurality of through-holes exposing the first front surface. The plurality of second chips are bonded to the device wafer, and the plurality of second chips are bonded with the adhesive layer to cover the plurality of first through-holes in a one-to-one correspondence.

A memory die including a three-dimensional array of memory elements and a logic die including a peripheral circuitry that support operation of the three-dimensional array of memory elements can be bonded by die-to-die bonding to provide a bonded assembly. External bonding pads for the bonded assembly can be provided by forming recess regions through the memory die or through the logic die to physically expose metal interconnect structures within interconnect-level dielectric layers. The external bonding pads can include, or can be formed upon, a physically exposed subset of the metal interconnect structures. Alternatively or additionally, laterally-insulated external connection via structures can be formed through the bonded assembly to multiple levels of the metal interconnect structures. Further, through-dielectric external connection via structures extending through a stepped dielectric material portion of the memory die can be physically exposed, and external bonding pads can be formed thereupon.

A modular superconducting quantum processor includes a first superconducting chip including a first plurality of qubits each having substantially a first resonance frequency and a second plurality of qubits each having substantially a second resonance frequency, the first resonance frequency being different from the second resonance frequency, and a second superconducting chip including a third plurality of qubits each having substantially the first resonance frequency and a fourth plurality of qubits each having substantially the second resonance frequency. The quantum processor further includes an interposer chip connected to the first superconducting chip and to the second superconducting chip. The interposer chip has interposer coupler elements configured to couple the second plurality of qubits to the fourth plurality of qubits.

A semiconductor device includes a first integrated circuit and a second integrated circuit. The first integrated circuit includes a semiconductor substrate and a dielectric layer disposed on a top surface of the semiconductor substrate. The second integrated circuit is disposed on the dielectric layer of the first integrated circuit and includes a dummy opening extending through the second integrated circuit and having a metal layer covering the inner walls of the dummy opening and in contact with the dielectric layer, wherein the metal layer is electrically grounded or electrically floating.

A display driver integrated circuit (IC) device includes a first substrate having a first front surface and a first back surface; a first interlayer insulating layer on the first front surface; a wiring layer in the first interlayer insulating layer; a first bonding insulating layer on the first interlayer insulating layer; a second substrate having a second front surface and a second back surface, the second front surface being disposed toward the first front surface; a second interlayer insulating layer on the second front surface a second bonding insulating layer on the second interlayer insulating layer and physically bonded to the first bonding insulating layer; and a back via stack structure penetrating the second substrate, the second interlayer insulating layer, the second bonding insulating layer, the first bonding insulating layer, and the first interlayer insulating layer and electrically connected to the wiring layer.

A manufacturing method of a semiconductor structure includes covering first and second semiconductor dies with an insulating encapsulant. The first semiconductor die includes an active surface accessibly exposed by the insulating encapsulant and a first conductive terminal distributed at the active surface. The second semiconductor die includes an active surface accessibly exposed by the insulating encapsulant and a second conductive terminal distributed at the active surface. A redistribution circuit layer is formed on the insulating encapsulant and the active surfaces of the first and second semiconductor dies. A conductive trace of the redistribution circuit layer is electrically connected from the first semiconductor die and meanderingly extends to the second semiconductor die, and a ratio of a total length of the conductive trace to a top width of the insulating encapsulant between the first and second semiconductor dies ranges from about 3 to about 10.

An integrated circuit is provided that comprises a first substrate having a plurality of conductive contact pads spaced apart from one another on a surface of the first substrate, a dielectric layer overlying the first substrate and the plurality of conductive contact pads, and a second substrate overlying the dielectric layer. A plurality of superconducting contacts extend through the second substrate and the dielectric layer to the first substrate, wherein each superconducting contact of the plurality of superconducting contacts is aligned with and in contact with a respective conductive contact pad of the plurality of conductive contact pads.

Various embodiments of the present application are directed towards a method for forming an integrated chip in which a group III-V device is bonded to a substrate, as well as the resulting integrated chip. In some embodiments, the method includes: forming a chip including an epitaxial stack, a metal structure on the epitaxial stack, and a diffusion layer between the metal structure and the epitaxial stack; bonding the chip to a substrate so the metal structure is between the substrate and the epitaxial stack; and performing an etch into the epitaxial stack to form a mesa structure with sidewalls spaced from sidewalls of the diffusion layer. The metal structure may, for example, be a metal bump patterned before the bonding or may, for example, be a metal layer that is on an etch stop layer and that protrudes through the etch stop layer to the diffusion layer.