Patent classifications
H01L2224/82132
Integrated fan-out package and manufacturing method thereof
An integrated fan-out (InFO) package includes a die, a plurality of conductive structures aside the die, an encapsulant laterally encapsulating the die and the conductive structure, and a redistribution structure. The redistribution structure is disposed on the encapsulant. The redistribution structure includes a plurality of routing patterns, a plurality of conductive vias, and a plurality of alignment marks. The routing patterns and the conductive vias are electrically connected to the die and the conductive structures. The alignment marks surround the routing patterns and the conductive vias. The alignment marks are electrically insulated from the die and the conductive structures. At least one of the alignment marks is in physical contact with the encapsulant, and vertical projections of the alignment marks onto the encapsulant have an offset from one another.
INTEGRATED FAN-OUT PACKAGE AND MANUFACTURING METHOD THEREOF
An integrated fan-out (InFO) package includes a die, an encapsulant laterally encapsulating the die, and a redistribution structure. The redistribution structure is disposed on the encapsulant. The redistribution structure includes a plurality of routing patterns and a plurality of alignment marks. The routing patterns are electrically connected to the die. The alignment marks surround the routing patterns. The alignment marks are electrically insulated from the die and the routing patterns. At least one of the alignment marks is in physical contact with the encapsulant, and the alignment marks located at different level heights are arranged in a non-overlapping manner vertically.
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES AND CORRESPONDING DEVICE
A semiconductor chip or die is mounted at a position on a support substrate. A light-permeable laser direct structuring (LDS) material is then molded onto the semiconductor chip positioned on the support substrate. The semiconductor chip is visible through the LDS material. Laser beam energy is directed to selected spatial locations of the LDS material to structure in the LDS material a pattern of structured formations corresponding to the locations of conductive lines and vias for making electrical connection to the semiconductor chip. The spatial locations of the LDS material to which laser beam energy is directed are selected as a function of the position the semiconductor chip which is visible through the LDS material, thus countering undesired effects of positioning offset of the chip on the substrate.
Multi-Chip Fan Out Package and Methods of Forming the Same
A package includes a die having a conductive pad at a top surface of the die, a stud bump over and connected to the conductive pad, and a redistribution line over and connected to the stud bump. An electrical connector is over and electrically coupled to the redistribution line.
Electronic module
The present invention relates to an electronic module. In particular, to an electronic module which includes one or more components embedded in an installation base. The electronic module can be a module like a circuit board, which includes several components, which are connected to each other electrically, through conducting structures manufactured in the module. The components can be passive components, microcircuits, semiconductor components, or other similar components. Components that are typically connected to a circuit board form one group of components. Another important group of components are components that are typically packaged for connection to a circuit board. The electronic modules to which the invention relates can, of course, also include other types of components.
Multi-chip fan out package and methods of forming the same
A package includes a die having a conductive pad at a top surface of the die, a stud bump over and connected to the conductive pad, and a redistribution line over and connected to the stud bump. An electrical connector is over and electrically coupled to the redistribution line.
Sensing die encapsulated by an encapsulant with a roughness surface having a hollow region
A semiconductor device includes an encapsulant including a first hollow region, a sensing die in the first hollow region of the encapsulant, and a redistribution structure disposed on the encapsulant and the sensing die and electrically coupled to the sensing die. A top width of the hollow region is greater than a bottom width of the hollow region. The redistribution structure includes a second hollow region which exposes a sensing area of the sensing die, and the redistribution structure is slanted downward from an edge of the device toward the sensing area.
Electronic module
The present invention relates to an electronic module. In particular, to an electronic module which includes one or more components embedded in an installation base. The electronic module can be a module like a circuit board, which includes several components, which are connected to each other electrically, through conducting structures manufactured in the module. The components can be passive components, microcircuits, semiconductor components, or other similar components. Components that are typically connected to a circuit board form one group of components. Another important group of components are components that are typically packaged for connection to a circuit board. The electronic modules to which the invention relates can, of course, also include other types of components.
MANUFACTURING METHOD OF SENSING DIE ENCAPSULATED BY ENCAPSULANT WITH ROUGHNESS SURFACE HAVING HOLLOW REGION
A manufacturing method of a semiconductor package includes: laterally covering a sensing die with an encapsulant, where the encapsulant includes a top surface and a rounded inner edge connected to the top surface, and a top surface of the sensing die is lower than the rounded inner edge of the encapsulant and is smoother than the top surface of the encapsulant; and forming a redistribution structure on the top surface of the encapsulant and the top surface of the sensing die.
Massively parallel transfer of microLED devices
MicroLED devices can be transferred in large numbers to form microLED displays using processes such as pick-and-place, thermal adhesion transfer, or fluidic transfer. A blanket solder layer can be applied to connect the bond pads of the microLED devices to the terminal pads of a support substrate. After heating, the solder layer can connect the bond pads with the terminal pads in vicinity of each other. The heated solder layer can correct misalignments of the microLED devices due to the transfer process.