A package includes a die having a conductive pad at a top surface of the die, a stud bump over and connected to the conductive pad, and a redistribution line over and connected to the stud bump. An electrical connector is over and electrically coupled to the redistribution line.

A package includes a die having a conductive pad at a top surface of the die, a stud bump over and connected to the conductive pad, and a redistribution line over and connected to the stud bump. An electrical connector is over and electrically coupled to the redistribution line.

In a mark forming step in a manufacturing method for a component incorporated substrate in which an electronic component is positioned with reference to a mark formed in a copper layer, when an imaginary line extending from a search center of a search range of a sensor, to an edge side of the search range is represented as a search reference line and an imaginary line extending, in a state in which a mark center, is matched with the search center, from the mark center in the same direction as the search reference line to an outer ridgeline of the mark is represented as a mark reference line, the mark formed in a shape in which the outer ridgeline of the mark is present in a position where a length of the mark reference line is in a range of 30% or more of the search reference line.

A manufacturing method for a component incorporated substrate according to the present invention includes positioning an electronic component with reference to a mark formed on a copper layer, the mark consisting of a material less easily etched than copper by a copper etching agent used for etching of copper, after mounting the electronic component on the copper layer with an adhesive layer interposed therebetween, embedding the electronic component and the mark in an insulating substrate, thereafter, etching and removing a part of the copper layer to form a window for exposing the mark, forming an LVH reaching a terminal of the electronic component with reference to the exposed mark, electrically connecting the terminal and the copper layer via a conduction via formed by applying copper plating to the LVH, and, thereafter, forming the copper layer into a wiring pattern.

An integrated fan-out (InFO) package includes a die, an encapsulant laterally encapsulating the die, and a redistribution structure. The redistribution structure is disposed on the encapsulant. The redistribution structure includes a plurality of routing patterns and a plurality of alignment marks. The routing patterns are electrically connected to the die. The alignment marks surround the routing patterns. The alignment marks are electrically insulated from the die and the routing patterns. At least one of the alignment marks is in physical contact with the encapsulant, and the alignment marks located at different level heights are arranged in a non-overlapping manner vertically.

An integrated fan-out (InFO) package includes a die, an encapsulant laterally encapsulating the die, and a redistribution structure. The redistribution structure is disposed on the encapsulant. The redistribution structure includes a plurality of routing patterns and a plurality of alignment marks. The routing patterns are electrically connected to the die. The alignment marks surround the routing patterns. The alignment marks are electrically insulated from the die and the routing patterns. At least one of the alignment marks is in physical contact with the encapsulant, and the alignment marks located at different level heights are arranged in a non-overlapping manner vertically.