A semiconductor device package includes a package substrate having a die attach region, a silicon carbide (SiC) substrate having a first surface including a semiconductor device layer thereon and a second surface that is opposite the first surface, and a die attach metal stack. The die attach metal stack includes a sputtered die attach material layer that attaches the second surface of the SiC substrate to the die attach region of the package substrate, where the sputtered die attach material layer comprises a void percent of about 15% or less. The sputtered die attach material layer may be formed using a sputter gas including at least one of krypton (Kr), xenon (Xe), or radon (Rn). The die attach metal stack may further include a metal interlayer that prevent contacts with a first barrier metal layer during a phase transition of the die attach material layer.

A method includes forming a transistor over a front side of a substrate, in which the transistor comprises a channel region, a gate region over the channel region, and source/drain regions on opposite sides of the gate region; forming a front-side interconnect structure over the transistor, wherein the front-side interconnect structure includes a dielectric layer and conductive features; and bonding the front-side interconnect structure to a carrier substrate via a bonding layer, in which the bonding layer is between the front-side interconnect structure and the carrier substrate, and the bonding layer has a higher thermal conductivity than the dielectric layer of the front-side interconnect structure.

Embodiments of bonded semiconductor structures and fabrication methods thereof are disclosed. In an example, a semiconductor device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first and second semiconductor structures. The first semiconductor structure includes a substrate, a first device layer disposed on the substrate, and a first bonding layer disposed above the first device layer and including a first bonding contact. The second semiconductor structure includes a second device layer, and a second bonding layer disposed below the second device layer and including a second bonding contact. The first bonding contact is in contact with the second bonding contact at the bonding interface. At least one of the first bonding contact and the second bonding contact includes a capping layer at the bonding interface and having a conductive material different from a remainder of the respective first or second bonding contact.

A method of soldering includes providing a substrate having a first metal joining surface, providing a semiconductor die having a second metal joining surface, providing a solder preform having a first interface surface and a second interface surface, arranging the solder preform between the substrate and the semiconductor die such that the first interface surface faces the first metal joining surface and such that the second interface surface faces the second metal joining surface, and performing a mechanical pressure-free diffusion soldering process that forms a soldered joint between the substrate and the semiconductor die by melting the solder preform and forming intermetallic phases in the solder. One or both of the first interface surface and the second interface surface has a varying surface profile that creates voids between the solder preform and one or both of the substrate and the semiconductor die before the melting of the solder preform.

In an example, a semiconductor device includes a first semiconductor structure including a memory array device, a second semiconductor structure including a peripheral device, and a bonding structure comprising a first bonding pad, a second bonding pad, and a remainder layer located between and in contact with the first and second bonding pad in a vertical direction. The first bonding pad is located between the remainder layer and the first semiconductor structure in the vertical direction. The second bonding pad is located between the remainder layer and the second semiconductor structure in the vertical direction. A conductive material of the remainder layer is cobalt metal different from the first and second bonding pads.

A semiconductor device package includes a package substrate having a die attach region, a silicon carbide (SiC) substrate having a first surface including a semiconductor device layer thereon and a second surface that is opposite the first surface, and a die attach metal stack. The die attach metal stack includes a sputtered die attach material layer that attaches the second surface of the SiC substrate to the die attach region of the package substrate, where the sputtered die attach material layer comprises a void percent of about 15% or less. The sputtered die attach material layer may be formed using a sputter gas including at least one of krypton (Kr), xenon (Xe), or radon (Rn). The die attach metal stack may further include a metal interlayer that prevent contacts with a first barrier metal layer during a phase transition of the die attach material layer.

Disclosed herein is a method of forming an electrical connecting structure having nano-twins copper. The method includes the steps of (i) forming a first nano-twins copper layer including a plurality of nano-twins copper grains; (ii) forming a second nano-twins copper layer including a plurality of nano-twins copper grains; and (iii) joining a surface of the first nano-twins copper layer with a surface of the second nano-twins copper layer, such that at least a portion of the first nano-twins copper grains grow into the second nano-twins copper layer, or at least a portion of the second nano-twins copper grains grow into the first nano-twins copper layer. An electrical connecting structure having nano-twins copper is provided as well.

A semiconductor device includes a single lead frame, a semiconductor element, and a mold material. The semiconductor element is joined onto one main surface of the lead frame. The lead frame includes a die-attach portion, a signal terminal portion, and a ground terminal portion. The die-attach portion, the signal terminal portion, and the ground terminal portion are disposed directly below the mold material so as to be arranged in a direction along one main surface. A groove portion is provided by partially removing the lead frame so as to allow the groove portion to pass therethrough, the groove portion being provided between the die-attach portion and the ground terminal portion adjacent to each other in the lead frame and between the signal terminal portion and the ground terminal portion adjacent to each other in the lead frame.

Production system for wafer bonding comprising modules for wet chemical wafer cleaning and surface passivation and vacuum modules with base pressure in the ultrahigh vacuum regime for the removal of surface passivation, wafer flipping and alignment, low temperature annealing and wafer bonding, with all modules integrated in the same tool and individually serviceable. Methods for oxide-free covalent semiconductor wafer bonding include wet chemistry and vacuum processing at low temperatures compatible with CMOS processed wafers.

A conductive plate has a front surface at a front side and a rear surface at a rear side. The front surface includes a first front surface on which a first arrangement region is disposed and a second front surface on which a second arrangement region is disposed. The first front surface has a height measured from the rear surface that is different from a height of the second front surface measured from the rear surface. Next, first and second bonding materials are respectively applied to the first and second arrangement regions. A first part is bonded to the first arrangement region via the first bonding material, and a second part is bonded to the second arrangement region via the second bonding material. The heights of the first and second arrangement regions set on the front surface on the conductive plate are different from each other.