Representative techniques provide process steps for forming a microelectronic assembly, including preparing microelectronic components such as dies, wafers, substrates, and the like, for bonding. One or more surfaces of the microelectronic components are formed and prepared as bonding surfaces. The microelectronic components are stacked and bonded without adhesive at the prepared bonding surfaces.

Package structure and method of manufacturing the same are provided. The package structure includes a first die, a second die, a first encapsulant, a bridge die, and a second encapsulant. The first encapsulant laterally encapsulates the first die and the second die. The bridge die is electrically connected to the first die and the second die. The second encapsulant is located over the first die, the second die and the first encapsulant, laterally encapsulating the bridge die and filling a space between the bridge die and the first die, between the bridge die and the first encapsulant and between the bridge die and the second die. A material of the second encapsulant is different from a material of the first encapsulant.

Representative implementations of techniques and methods include processing singulated dies in preparation for bonding. A plurality of semiconductor die components may be singulated from a wafer component, the semiconductor die components each having a substantially planar surface. Particles and shards of material may be removed from edges of the plurality of semiconductor die component. Additionally, one or more of the plurality of semiconductor die components may be bonded to a prepared bonding surface, via the substantially planar surface.

A stacked device includes a stacked structure in which a plurality of semiconductors are electrically connected to each other, the semiconductor includes a surface on which a plurality of terminals are provided, the plurality of terminals include a terminal that bonds and electrically connects the semiconductors to each other and a terminal that bonds the semiconductors to each other and does not electrically connect the semiconductors to each other, an area ratio of the plurality of terminals on the surface of the semiconductor is 40% or higher, and an area ratio of the terminals that bond and electrically connect the semiconductors to each other among the plurality of terminals is lower than 50%.

A method of forming a solar cell device that includes forming a porous layer in a monocrystalline donor substrate and forming an epitaxial semiconductor layer on the porous layer. A solar cell structure is formed on the epitaxial semiconductor layer. A carrier substrate is bonded to the solar cell structure through a bonding layer. The monocrystalline donor substrate is removed by cleaving the porous layer. A grid of metal contacts is formed on the epitaxial semiconductor layer. The exposed portions of the epitaxial semiconductor layer are removed. The exposed surface of the solar cell structure is textured. The textured surface may be passivated, in which the passivated surface can provide an anti-reflective coating.

Embodiments of bonded semiconductor structures and fabrication methods thereof are disclosed. In an example, a method for forming a semiconductor device is disclosed. A first device layer is formed on a first substrate. A first bonding layer including a first bonding contact is formed above the first device layer. A first capping layer is formed at an upper end of the first bonding contact. The first capping layer has a conductive material different from a remainder of the first bonding contact. A second device layer is formed on a second substrate. A second bonding layer including a second bonding contact is formed above the second device layer. The first substrate and the second substrate are bonded in a face-to-face manner, so that the first bonding contact is in contact with the second bonding contact by the first capping layer.

Implanting ions to form a cleave layer in a semiconductor device causes damage to sensitive materials such as high-K dielectrics. In a process for forming a cleave layer and repairing damage caused by ion implantation, ions are implanted through a circuit layer of a substrate to form a cleave plane. The substrate is exposed to a hydrogen gas mixture for a first time at a first temperature to repair damage caused by the implanted ions. A cleaving process may then be performed, and the cleaved substrate may be stacked in a 3DIC structure.

Representative techniques provide process steps for forming a microelectronic assembly, including preparing microelectronic components such as dies, wafers, substrates, and the like, for bonding. One or more surfaces of the microelectronic components are formed and prepared as bonding surfaces. The microelectronic components are stacked and bonded without adhesive at the prepared bonding surfaces.

Representative implementations of techniques and methods include processing singulated dies in preparation for bonding. A plurality of semiconductor die components may be singulated from a wafer component, the semiconductor die components each having a substantially planar surface. Particles and shards of material may be removed from edges of the plurality of semiconductor die component. Additionally, one or more of the plurality of semiconductor die components may be bonded to a prepared bonding surface, via the substantially planar surface.

An integrated circuit packaging method, including: a top surface of a substrate, a bottom surface of the substrate, or the interior of the substrate is provided with circuit layers, and the circuit layers are provided with circuit pins; a component element is mounted on the substrate, and a surface of the component element facing the substrate is provided with component pins; connection through holes are formed on the substrate, the connection through holes are made to abut on the circuit pins, and a first opening of the connection through holes is abutted on the component pins; conductive layers are fabricated inside of the connection through holes by means of a second opening of the connection through holes, and the conductive layers electrically connect the component pins with the circuit pins.