Patent classifications
H01L2224/83047
HETEROGENOUS INTEGRATION SCHEME FOR III-V/Si AND Si CMOS INTEGRATED CIRCUITS
A method includes bonding a III-V die directly to a Complementary Metal-Oxide-Semiconductor (CMOS) die to form a die stack. The III-V die includes a (111) semiconductor substrate, and a first circuit including a III-V based n-type transistor formed at a surface of the (111) semiconductor substrate. The CMOS die includes a (100) semiconductor substrate, and a second circuit including an n-type transistor and a p-type transistor on the (100) semiconductor substrate. The first circuit is electrically connected to the second circuit.
SEMICONDUCTOR PACKAGE AND METHODS OF MANUFACTURING THE SAME
A semiconductor package includes an interconnect substrate, a semiconductor die, and an underfill. The semiconductor die is disposed over the interconnect substrate and has a first top surface extends along a first direction. The underfill includes a body portion and an extending portion. The body portion is disposed between the interconnect substrate and the semiconductor die. The extending portion connects to the body portion, where the extending portion is next to the semiconductor die and has a second top surface extends along the first direction.