A wafer to wafer bonding method includes performing a plasma process on a bonding surface of a first wafer, pressurizing the first wafer after performing the plasma process on the bonding surface of the first wafer, and bonding the first wafer to a second wafer. The plasma process has different plasma densities along a circumferential direction about a center of the first wafer. A middle portion of the first wafer protrudes after pressurizing the first wafer. The first wafer is bonded to the second wafer by gradually joining the first wafer to the second wafer from the middle portion of the first wafer to a peripheral region of the first wafer.

A multi-layer wafer and method of manufacturing such wafer are provided. The method includes creating under bump metallization (UMB) pads on each of the two heterogeneous wafers; applying a conductive means above the UMB pads on at least one of the two heterogeneous wafers; and low temperature bonding the two heterogeneous wafers to adhere the UMB pads together via the conductive means. At least one stress compensating polymer layer may be applied to at least one of two heterogeneous wafers. The multi-layer wafer comprises two heterogeneous wafers, each of the heterogeneous wafer having UMB pads and at least one of the heterogeneous wafers having a stress compensating polymer layer and a conductive means applied above the UMB pads on at least one of the two heterogeneous wafers. The two heterogeneous wafers low temperature bonded together to adhere the UMB pads together via the conductive means.

A die placement and coupling apparatus may include a die bonding attachment. The die placement and coupling apparatus may include a compliant head unit that may be adapted to optionally couple with a semiconductor die. The compliant head unit may include a die attach surface that may include a layer of compliant material. The layer of compliant material may be coupled to the compliant head unit. The die attach surface may be adapted to mate with the semiconductor die when the semiconductor die is coupled with the compliant head unit. The layer of compliant material may be adapted to yield in response to an applied force. The die placement and coupling apparatus may include a vacuum port in communication with the die attach surface. The port may be adapted to have a vacuum applied to the port, and the vacuum temporarily holds the semiconductor die to the die attach surface.

A method of forming a semiconductor structure is provided. Two wafers are first bonded by oxide bonding. Next, the thickness of a first wafer is reduced using an ion implantation and separation approach, and a second wafer is thinned by using a removal process. First devices are formed on the first wafer, and a carrier is then attached over the first wafer, and an alignment process is performed from the bottom of the second wafer to align active regions of the second wafer for placement of the second devices with active regions of the first wafer for placement of the first devices. The second devices are then formed in the active regions of the second wafer. Furthermore, a via structure is formed through the first wafer, the second wafer and the insulation layer therebetween to connect the first and second devices on the two sides of the insulation layer.

In an embodiment, a method includes: connecting a light emitting diode to a substrate; encapsulating the light emitting diode with a photosensitive encapsulant; forming a first opening through the photosensitive encapsulant adjacent the light emitting diode; and forming a conductive via in the first opening.

A semiconductor device includes: a substrate; a semiconductor chip disposed adjacent to a front surface of the semiconductor substrate; an adhesive fixing a back surface of the semiconductor chip to the front surface of the substrate; and a plurality of spacers disposed to regulate a distance between the substrate and the semiconductor chip. The spacers are bonded to the front surface of the substrate or the back surface of the semiconductor chip, and are located on respective vertexes of a polygon surrounding a center of gravity of the semiconductor chip.

A stacked device includes a stacked structure in which a plurality of semiconductors are electrically connected to each other, the semiconductor includes a surface on which a plurality of terminals are provided, the plurality of terminals include a terminal that bonds and electrically connects the semiconductors to each other and a terminal that bonds the semiconductors to each other and does not electrically connect the semiconductors to each other, an area ratio of the plurality of terminals on the surface of the semiconductor is 40% or higher, and an area ratio of the terminals that bond and electrically connect the semiconductors to each other among the plurality of terminals is lower than 50%.

The disclosure is provided with: a temporary crimping step in which one or more semiconductor chips 10 are sequentially laminated while being temporarily crimped in each of two or more locations on a substrate 30 to thereby form chip stacks ST in a temporarily crimped state; and a permanent crimping step in which the top surfaces of all of the chip stacks ST formed in the temporarily crimped state are sequentially heated, pressurized, and permanently crimped. Furthermore, a specifying step is provided prior to the temporary crimping step for specifying a separation distance Dd which is the distance from the chip stacks ST under permanent crimping to a location at which the temperature of the substrate 30, the temperature having been raised by heating for the permanent crimping, becomes less than or equal to a prescribed permissible temperature Td, and in the temporary crimping step, the chip stacks ST in the temporarily crimped state are formed separated from each other by the separation distance Dd or more.

A package manufacturing having a semiconductor substrate, a bonding layer, at least one semiconductor device, a redistribution circuit structure and an insulating encapsulation. The bonding layer is disposed on the semiconductor substrate. The semiconductor device is disposed on and in contact with a portion of the bonding layer, wherein the bonding layer is located between the semiconductor substrate and the semiconductor device and adheres the semiconductor device onto the semiconductor substrate. The redistribution circuit structure is disposed on and electrically connected to the semiconductor device, wherein the semiconductor device is located between the redistribution circuit structure and the bonding layer. The insulating encapsulation wraps a sidewall of the semiconductor device, wherein a sidewall of the bonding layer is aligned with a sidewall of the insulating encapsulation and a sidewall of the redistribution circuit structure.

The system and method for a heterogeneous integrated circuit packaging method having an air-cavity lid to protect the active face of an integrated circuit, or other device, either active or passive, from the environment. The packaging is hermetic or near hermetic. In some examples, the cover provides electrical routing. In some examples, the cover also provides electromagnetic shielding. In some cases, an encapsulant and/or an overmoulding is provided to further protect the heterogeneous integrated circuit.