Even in case of conductive particles being clamped between stepped sections of substrate electrodes and electrode terminals, conductive particles sandwiched between each main surface of the substrate electrodes and electrode terminals are sufficiently compressed, ensuring electrical conduction. An electronic component is connected to a circuit substrate via an anisotropic conductive adhesive agent, on respective edge-side areas of substrate electrodes of the circuit substrate and electrode terminals of the electronic component, stepped sections are formed and abutted, conductive particles are sandwiched between each main surface and stepped sections of the substrate electrodes and electrode terminals; the conductive particles and stepped sections satisfy formula, a+b+c0.8 D (1), wherein a is height of the stepped section of the electrode terminals, b is height of the stepped section of the substrate electrodes, c is gap distance between each stepped sections and D is diameter of conductive particles.

A method of fabricating a semiconductor chip includes the following steps. A bonding material layer is formed on a first wafer substrate and is patterned to form a first bonding layer having a strength adjustment pattern. A semiconductor component layer and a first interconnect structure layer are formed on a second wafer substrate. The first interconnect structure layer is located. A second bonding layer is formed on the first interconnect structure layer. The second wafer substrate is bonded to the first wafer substrate by contacting the second bonding layer with the first bonding layer. A bonding interface of the second bonding layer and the first bonding layer is smaller than an area of the second bonding layer. A second interconnect structure layer is formed on the semiconductor component layer. A conductor terminal is formed on the second interconnect structure layer.

A bonding apparatus 10 includes: a bonding head 18 configured to move a top camera 24 facing toward a bonding surface and a collet 22 disposed with an offset from the top camera 24, while integrally holding the top camera 24 and the collet 22; a bottom camera 28 facing toward the collet 22 so as to detect a position of a semiconductor chip 100 held by the collet 22 with respect to the collet 22; a reference mark 32 disposed within a view field of the bottom camera 28; and a control unit 40. The control unit 40 moves the bonding head 18 based on a position of the mark 32 recognized by the top camera 24, and then calculates a value of the offset based on a position of the collet 22 with respect to the mark 32 recognized by the bottom camera 28. With this, it is possible to provide a bonding apparatus capable of easily detecting an offset between a bonding tool and a position detection camera without providing a dedicated camera.

According to an aspect of the present principles, methods are provided for fabricating an integrated structure. A method includes forming a very large scale integration (VLSI) structure including a semiconductor layer at a top of the VLSI structure. The method further includes mounting the VLSI structure to a support structure. The method additionally includes removing at least a portion of the semiconductor layer from the VLSI structure. The method also includes attaching an upper layer to the top of the VLSI structure. The upper layer is primarily composed of a material that has at least one of a higher resistivity or a higher transparency than the semiconductor layer. The upper layer includes at least one hole for at least one of a photonic device or an electronic device. The method further includes releasing said VLSI structure from the support structure.

A press fitting head comprising an elastic member in a part where the press fitting head contacts a semiconductor device, and an alignment mark recognition area capable of detecting an optically readable marker provided on a surface to be contacted to the semiconductor device is provided. Additionally, a semiconductor manufacturing apparatus in which the press fitting head is applied is provided.

A laminated chip includes: semiconductor chips that are laminated; and multiple types of adhesive insulating resin films that include mutually different characteristics and that are filled between the semiconductor chips, wherein the multiple types of the adhesive insulating resin films are arranged in a chip plane direction, depending on a demand characteristic for each region in a chip plane.

According to an aspect of the present principles, methods are provided for fabricating an integrated structure. A method includes forming a very large scale integration (VLSI) structure including a semiconductor layer at a top of the VLSI structure. The method further includes mounting the VLSI structure to a support structure. The method additionally includes removing at least a portion of the semiconductor layer from the VLSI structure. The method also includes attaching an upper layer to the top of the VLSI structure. The upper layer is primarily composed of a material that has at least one of a higher resistivity or a higher transparency than the semiconductor layer. The upper layer includes at least one hole for at least one of a photonic device or an electronic device. The method further includes releasing said VLSI structure from the support structure.

This chip mounting system simultaneously images an alignment mark disposed on a substrate (WT) and an alignment mark disposed on a chip (CP), with the alignment marks disposed on the substrate (WT) and the chip (CP) being separated by a first distance at which the alignment marks fall within a depth-of-field range of imaging devices. The chip mounting system calculates a relative positional deviation amount between the substrate (WT) and the chip (CP) from the imaged images of the alignment marks imaged by the imaging devices and, based on the calculated positional deviation amount, relatively moves the chip (CP) with respect to the substrate (WT) in a direction in which the positional deviation amount therebetween decreases.

A method of manufacturing a substrate layered body includes: a step of applying a bonding material to the surface of at least one of a first substrate or a second substrate; a step of curing the bonding material applied on the surface to form a bonding layer having a reduced modulus at 23 C. of 10 GPa or less; and a step of bonding the first substrate and the second substrate via the bonding layer formed.

A semiconductor-device mounting structure includes a first semiconductor device and a plate-shaped second semiconductor device connected to the first semiconductor device. The first semiconductor device includes a flexible board, an electronic component, and a sealing resin. The flexible board includes a bendable flexible portion and a hard portion. The flexible portion is bent at a boundary with the hard portion, along a shape of the electronic component such that the flexible board covers the electronic component. The flexible board and the electronic component are sealed with the sealing resin. The first semiconductor device is provided vertical to the second semiconductor device such that the hard portion is provided parallel to the second semiconductor device, and a length of the hard portion in a direction perpendicular to a bend line of the flexible portion is equal to a thickness of a bottom surface of the electronic component in the direction.