This chip mounting system simultaneously images an alignment mark disposed on a substrate (WT) and an alignment mark disposed on a chip (CP), with the alignment marks disposed on the substrate (WT) and the chip (CP) being separated by a first distance at which the alignment marks fall within a depth-of-field range of imaging devices (35a, 35b). The chip mounting system calculates a relative positional deviation amount between the substrate (WT) and the chip (CP) from the imaged images of the alignment marks imaged by the imaging devices (35a, 35b) and, based on the calculated positional deviation amount, relatively moves the chip (CP) with respect to the substrate (WT) in a direction in which the positional deviation amount therebetween decreases.

This mounting device (100) comprises: a base (10) that moves linearly in relation to a substrate (16); a bonding head (20) that is attached to the base (10); a camera (25) that is attached to the base (10) and identifies the position of the substrate (16); a linear scale (33) having a plurality of graduations along the movement direction; a bonding head-side encoder head (31); and a camera-side encoder head (32). A control unit (50) causes the base (10) to move to a position where the bonding head-side encoder head (31) detects the position of a graduation. Due to this configuration, positioning accuracy of a semiconductor die (15) in relation to the substrate (16) is improved.

The present publication discloses a method for manufacturing a circuit-board structure. In the method, a conductor layer is made, which comprises a conductor foil and a conductor pattern on the surface of the conductor foil. A component is attached to the conductor layer and the conductor layer is thinned, in such a way that the conductor material of the conductor layer is removed from outside the conductor pattern.

Packaging method for forming the panel-level chip device is provided. The panel-level chip device includes a plurality of first bare chips disposed on a supporting base, and a plurality of first connection pillars. The panel-level chip device also includes a first encapsulation layer, and a first redistribution layer. The first redistribution layer includes a plurality of first redistribution elements and a plurality of second redistribution elements. Further, the panel-level chip device includes a solder ball group including a plurality of first solder balls. First connection pillars having a same electrical signal are electrically connected to each other by a first redistribution element. Each of remaining first connection pillars is electrically connected to one second redistribution element. The one second redistribution element is further electrically connected to a first solder ball of the plurality of first solder balls.

The invention provides an array substrate and chip bonding method, the array substrate comprising: an active area, and a bonding area located around the active area, wherein the bonding area is provided with an input terminal group, a first output terminal group and a second output terminal a group; the first output terminal group is located at a side of the input terminal group away from the active area, and the second output terminal group is located between the first output terminal group and the input terminal group; when bonding chips, the first output terminal group or the second output terminal group is selected to cooperate with the input terminal group for chip bonding according to the chip type. By simultaneously providing the first and second output terminal groups, the bonding of the second type chip increases the distance between the chip and the edge of the array substrate.

According to one embodiment, a display device includes a display panel including a first substrate, and a wiring board mounted on a mounting portion of the first substrate. The display panel includes a first terminal and a second terminal located in the mounting portion, a first alignment mark located in the mounting portion and located between the first terminal and the second terminal, a first wiring line connected to the first terminal, and a second wiring line connected to the second terminal. The wiring board includes a first connection wiring line connected to the first terminal, a second connection wiring line connected to the second terminal, and a second alignment mark located between the first connection wiring line and the second connection wiring line.

A semiconductor package is disclosed. The disclosed semiconductor package includes a substrate having bonding pads at an upper surface thereof, a lower semiconductor chip, at least one upper semiconductor chip disposed on the lower semiconductor chip, and a dam structure having a closed loop shape surrounding the lower semiconductor chip. The dam structure includes narrow and wide dams disposed between the lower semiconductor chip and the bonding pads. The wide dam has a greater inner width than the narrow dam. The semiconductor packages further includes an underfill disposed inside the dam structure and being filled between the substrate and the lower semiconductor chip.

A semiconductor package and a method of manufacturing the same are provided. The semiconductor package includes a semiconductor die, a cap layer, a conductive terminal, and a dam structure. The semiconductor die has a first surface. The cap layer is over the semiconductor die and has a second surface facing the first surface of the semiconductor die. The conductive terminal penetrates the cap layer and electrically connects to the semiconductor die. The dam structure is between the semiconductor die and the cap layer and surrounds a portion of the conductive terminal between the first surface and the second surface, thereby forming a gap between the cap layer and the semiconductor die.

A method of fabricating a display device may include disposing a display panel on a stage to be parallel to an XZ-plane defined by a horizontal X-axis and a vertical Z-axis, measuring a height of a first side surface of the display panel in a direction of the Z-axis, rotating the stage such that the first side surface is parallel to a reference horizontal line in case that a result of the measured height indicates that the first side surface includes an inclined surface, moving the display panel in a direction of the Z-axis such that a first pad disposed on the first side surface overlaps the reference horizontal line, and bonding a second pad of a printed circuit board with the first pad.

An alignment mark at a position that overlaps an area in which an anisotropic conductive film is pasted, and to accurately perform alignment using an image captured by a camera. An alignment method in which an electronic component is mounted on the obverse surface of a transparent substrate with a conductive adhesive agent interposed therebetween, a substrate-side alignment mark and a component-side alignment mark are adjusted from the captured image, and the position at which the electronic component is mounted on the transparent substrate is aligned, wherein in the conductive adhesive agent, conductive particles are in a regular arrangement as viewed from a planar perspective, and in the captured image, the outside edges of the alignment marks exposed between the conductive particles are intermittently visible as line segments (S) along the imaginary line segments of the outside edges of the alignment mark.