A stacked device includes a stacked structure in which a plurality of semiconductors are electrically connected to each other, the semiconductor includes a surface on which a plurality of terminals are provided, the plurality of terminals include a terminal that bonds and electrically connects the semiconductors to each other and a terminal that bonds the semiconductors to each other and does not electrically connect the semiconductors to each other, an area ratio of the plurality of terminals on the surface of the semiconductor is 40% or higher, and an area ratio of the terminals that bond and electrically connect the semiconductors to each other among the plurality of terminals is lower than 50%.

Method and system that operates on a server include a time and expense management interface for capturing time and expense reporting. The time and expense reporting is for utility distribution systems, such as electrical power distribution and/or transmission systems, cellular, telecommunications, cable TV, water and sewer, natural gas, and others. These utility distribution systems include a large number of devices or objects that are distributed across a big geographic area. In one example, the authorization to submit the invoice for portions of the mobilization work order that have completed the approval process includes only authorization to submit the invoice for those portions of the mobilization work order i) not already paid or ii) that have been previously submitted and completed the approval process. The invention helps to document time and expense for government agencies, such as public utility commissions. This documentation maybe used with setting special charges on customer invoices.

In accordance with some embodiments of the present disclosure, an integrated fan-out (INFO) package includes a substrate, a molding compound, a buffer layer, a first chip, a second chip, and a redistribution circuit structure layer. The molding compound is disposed on the substrate. The buffer layer is disposed on the substrate and includes a first buffer pattern and a second pattern separated from the first buffer pattern by a distance. A thickness of the first buffer pattern is greater than a thickness of the second buffer pattern. The first chip is attached to the substrate through the first buffer pattern and surrounded by the molding compound. The second chip is attached to the substrate through the second buffer pattern and surrounded by the molding compound. The redistribution circuit structure layer is disposed on the molding compound and electrically connected to the first chip and the second chip.

The disclosure is provided with: a temporary crimping step in which one or more semiconductor chips 10 are sequentially laminated while being temporarily crimped in each of two or more locations on a substrate 30 to thereby form chip stacks ST in a temporarily crimped state; and a permanent crimping step in which the top surfaces of all of the chip stacks ST formed in the temporarily crimped state are sequentially heated, pressurized, and permanently crimped. Furthermore, a specifying step is provided prior to the temporary crimping step for specifying a separation distance Dd which is the distance from the chip stacks ST under permanent crimping to a location at which the temperature of the substrate 30, the temperature having been raised by heating for the permanent crimping, becomes less than or equal to a prescribed permissible temperature Td, and in the temporary crimping step, the chip stacks ST in the temporarily crimped state are formed separated from each other by the separation distance Dd or more.

The system and method for a heterogeneous integrated circuit packaging method having an air-cavity lid to protect the active face of an integrated circuit, or other device, either active or passive, from the environment. The packaging is hermetic or near hermetic. In some examples, the cover provides electrical routing. In some examples, the cover also provides electromagnetic shielding. In some cases, an encapsulant and/or an overmoulding is provided to further protect the heterogeneous integrated circuit.

The system and method for a heterogeneous integrated circuit packaging method having an air-cavity lid to protect the active face of an integrated circuit, or other device, either active or passive, from the environment. The packaging is hermetic or near hermetic. In some examples, the cover provides electrical routing. In some examples, the cover also provides electromagnetic shielding. In some cases, an encapsulant and/or an overmoulding is provided to further protect the heterogeneous integrated circuit.

A flexible multilayer construction (100) for mounting a light emitting semiconductor device (200) (LESD), includes a flexible dielectric substrate (110) having an LESD mounting region (120), first and second electrically conductive pads (130, 140) disposed in the LESD mounting region for electrically connecting to corresponding first and second electrically conductive terminals of an LESD (200) received in the LESD mounting region, and a first fiducial alignment mark (150) for an accurate placement of an LESD in the LESD mounting region. The first fiducial alignment mark is disposed within the LESD mounting region.

A mounting component includes a main body and a metal layer. The main body has a first main surface and a second main surface. The metal layer is arranged on the first main surface of the main body. The metal layer includes at least one concave recognition mark having an inclined surface that is inclined with respect to a main surface of the metal layer.

A method of semiconductor wafer bonding and system thereof are proposed. A first alignment mark of a first semiconductor wafer is aligned with a second alignment mark of a second semiconductor wafer. A partial attachment is performed between the first semiconductor wafer and the second semiconductor wafer. A scanning is performed along a direction substantially parallel to a surface of the first semiconductor wafer. It is determined if a bonding defect of the partially attached first semiconductor wafer and the second semiconductor wafer exists.

Processes for automatic registration between a solid circuit die and electrically conductive interconnects, and articles or devices made by the same are provided. The solid circuit die is disposed on a substrate with contact pads aligned with channels on the substrate. Electrically conductive traces are formed by flowing a conductive liquid in the channels toward the contact pads to obtain the automatic registration.