A method of fabricating a semiconductor chip includes the following steps. A bonding material layer is formed on a first wafer substrate and is patterned to form a first bonding layer having a strength adjustment pattern. A semiconductor component layer and a first interconnect structure layer are formed on a second wafer substrate. The first interconnect structure layer is located. A second bonding layer is formed on the first interconnect structure layer. The second wafer substrate is bonded to the first wafer substrate by contacting the second bonding layer with the first bonding layer. A bonding interface of the second bonding layer and the first bonding layer is smaller than an area of the second bonding layer. A second interconnect structure layer is formed on the semiconductor component layer. A conductor terminal is formed on the second interconnect structure layer.

A circuit board and a smart card module and a smart card employing the circuit board are provided. The circuit board includes a substrate and a pad region provided on the substrate. The pad region is configured for mounting an electronic component, and comprises a plurality of pads spaced from each other and traces connected to their respective pads. At least one of the pads has an arc edge. In the present invention, the distance between the pads is easy to be controlled during fabrication, and the stability of the adhesion between the chip and pad region is enhanced.

Panel level packaging (PLP) with high accuracy and high scalability is disclosed. The PLP employs an alignment carrier with a low coefficient of expansion which is configured with die regions having local die alignment marks. For example, local die alignment marks are provided for each die attach region. Depending on the size of the panel, it may be segmented into blocks, each with die regions with local die alignment marks. In addition, a block includes an alignment die region configured for attaching an alignment die. Linear and non-linear positional errors are reduced due to local die alignment marks and alignment dies. The use of local die alignment marks and alignment dies results in increase yields as well as scaling, thereby improving throughput and decreasing overall costs.

A lead frame with an IC chip pad with an alignment notch. A method of mounting a packaged IC chip on a lead frame at a precise angle by aligning a corner of the packaged IC chip to an alignment notch on the lead frame.

A lead frame with an IC chip pad with an alignment notch. A method of mounting a packaged IC chip on a lead frame at a precise angle by aligning a corner of the packaged IC chip to an alignment notch on the lead frame.

The present publication discloses a method for manufacturing a circuit-board structure. In the method, a conductor layer is made, which comprises a conductor foil and a conductor pattern on the surface of the conductor foil. A component is attached to the conductor layer and the conductor layer is thinned, in such a way that the conductor material of the conductor layer is removed from outside the conductor pattern.

A method of manufacturing a substrate layered body includes: a step of applying a bonding material to the surface of at least one of a first substrate or a second substrate; a step of curing the bonding material applied on the surface to form a bonding layer having a reduced modulus at 23° C. of 10 GPa or less; and a step of bonding the first substrate and the second substrate via the bonding layer formed.

A method of manufacturing a multi-layer wafer is provided. Under bump metallization (UMB) pads are created on each of two heterogeneous wafers. A conductive means is applied above the UMB pads on at least one of the two heterogeneous wafers. The two heterogeneous wafers are low temperature bonded to adhere the UMB pads together via the conductive means. At least one stress compensating polymer layer may be applied to at least one of two heterogeneous wafers. The stress compensating polymer layer has a polymer composition of a molecular weight polymethylmethacrylate polymer at a level of 10-50% with added liquid multifunctional acrylates forming the remaining 50-90% of the polymer composition.

A bonding apparatus and method includes: a stage configured to fix a first electric component; a pressing unit configured to press a conductive adhesive film and a second electric component onto the first electric component; a driver configured to control movement of the pressing unit along a direction; and a plurality of sensors at different positions on the stage and configured to sense a change in capacitance with the pressing unit, wherein the pressing unit includes a flat metal material in first regions facing the plurality of sensors.

A semiconductor package includes a metallic pad and leads, a semiconductor die including a semiconductor substrate attached to the metallic pad, and a conductor including a sacrificial fuse element above the semiconductor substrate, the sacrificial fuse element being electrically coupled between one of the leads and at least one terminal of the semiconductor die, a shock-absorbing material over a profile of the sacrificial fuse element, and mold compound covering the semiconductor die, the conductor, and the shock-absorbing material, and partially covering the metallic pad and leads, with the metallic pad and the leads exposed on an outer surface of the semiconductor package. Either a glass transition temperature of the shock-absorbing material or a melting point of the shock-absorbing material is lower than a melting point of the conductor.