Various embodiments of the teachings herein include a semifinished product for use in the populating of a power electronics component by a connecting method. The product includes an electrically insulating prepreg frame electrically insulated. The prepreg frame is configured for surrounding an applied connecting material at a metallized installation site during the population. A material of the prepreg frame enables simultaneous processability of electrical connection and electrical insulation by compression of the insulation material in the form of the semifinished product since the processing parameters of the electrical connecting material and the semifinished product are compatible.

Various embodiments of the teachings herein include a semifinished product for use in the populating of a power electronics component by a connecting method. The product includes an electrically insulating prepreg frame electrically insulated. The prepreg frame is configured for surrounding an applied connecting material at a metallized installation site during the population. A material of the prepreg frame enables simultaneous processability of electrical connection and electrical insulation by compression of the insulation material in the form of the semifinished product since the processing parameters of the electrical connecting material and the semifinished product are compatible.

A collet for compressing an adhesive-attached chip, the collet including a main body having a first pressing surface to which a pressing force from a compressing device is directly transmitted, and a projecting portion projecting from the main body and having a second pressing surface provided along an outer circumference of the first pressing surface, the first pressing surface and the second pressing surface forming a holding surface for holding the adhesive-attached chip.

A collet for compressing an adhesive-attached chip, the collet including a main body having a first pressing surface to which a pressing force from a compressing device is directly transmitted, and a projecting portion projecting from the main body and having a second pressing surface provided along an outer circumference of the first pressing surface, the first pressing surface and the second pressing surface forming a holding surface for holding the adhesive-attached chip.

A package that includes a substrate, an integrated device, a first encapsulation layer and a void. The substrate includes a first surface. The integrated device is coupled to the first surface of the substrate. The first encapsulation layer is located over the first surface of the substrate and the integrated device. The first encapsulation layer includes an undercut relative to a side surface of the integrated device. The void is located between the integrated device and the first surface of the substrate. The void is laterally surrounded by the undercut of the encapsulation layer.

A die bonding structure is provided. The die bonding structure includes a chip, an adhesive layer under the chip, a bonding layer under the adhesive layer, and a heat dissipation substrate under the bonding layer. The bonding layer includes a silver nano-twinned thin film, which has parallel-arranged twin boundaries. The parallel-arranged twin boundaries include at least 90% of [111] crystal orientation.

A die bonding structure is provided. The die bonding structure includes a chip, an adhesive layer under the chip, a bonding layer under the adhesive layer, and a heat dissipation substrate under the bonding layer. The bonding layer includes a silver nano-twinned thin film, which has parallel-arranged twin boundaries. The parallel-arranged twin boundaries include at least 90% of [111] crystal orientation.

In a general aspect, an apparatus can include an inner package including a first silicon carbide die having a die gate conductor coupled to a common gate conductor, and a second silicon carbide die having a die gate conductor coupled to the common gate conductor. The apparatus can include an outer package including a substrate coupled to the common gate conductor, and a clip coupled to the inner package and coupled to the substrate.

A method includes forming a solder layer on a surface of one or more chips. A lid is positioned over the solder layer on each of the one or more chips. Heat and pressure are applied to melt the solder layer and attach each lid to a corresponding solder layer. The solder layer has a thermal conductivity of ≥50 W/mK.

A method includes forming a solder layer on a surface of one or more chips. A lid is positioned over the solder layer on each of the one or more chips. Heat and pressure are applied to melt the solder layer and attach each lid to a corresponding solder layer. The solder layer has a thermal conductivity of ≥50 W/mK.