H01L2224/83486

SEMICONDUCTOR PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

A semiconductor package structure including a circuit substrate, a redistribution layer, and at least two dies is provided. The circuit substrate has a first surface and a second surface opposite the first surface. The redistribution layer is located on the first surface. The redistribution layer is electrically connected to the circuit substrate. The spacing of the opposing sidewalls of the redistribution layer is less than the spacing of the opposing sidewalls of the circuit substrate. The redistribution layer is directly in contact with the circuit substrate. At least two dies are disposed on the redistribution layer. Each of the at least two dies has an active surface facing the circuit substrate. One of the at least two dies is electrically connected to the other of the at least two dies by the redistribution layer. A manufacturing method of a semiconductor package structure is also provided.

PACKAGES FOR ADVANCED ANTENNA SYSTEMS
20210050650 · 2021-02-18 ·

System-in-package (SiP) devices are disclosed that include power amplifiers and controllers such as beamformer integrated circuits that are packaged together. Packaging and thermal management configurations are disclosed that allow a plurality of power amplifiers and a beamformer integrated circuit to operate efficiently while in close proximity to one another. SiP devices are disclosed that include heat spreaders that are incorporated within the SiP devices and exposed at top surfaces of the SiP devices to effectively dissipate heat. Heat spreaders may be provided as part of a lead frame that allows multiple SiP devices to be uniformly assembled with dimensions sized for high frequency applications, including millimeter wave operation.

PACKAGES FOR ADVANCED ANTENNA SYSTEMS
20210050650 · 2021-02-18 ·

System-in-package (SiP) devices are disclosed that include power amplifiers and controllers such as beamformer integrated circuits that are packaged together. Packaging and thermal management configurations are disclosed that allow a plurality of power amplifiers and a beamformer integrated circuit to operate efficiently while in close proximity to one another. SiP devices are disclosed that include heat spreaders that are incorporated within the SiP devices and exposed at top surfaces of the SiP devices to effectively dissipate heat. Heat spreaders may be provided as part of a lead frame that allows multiple SiP devices to be uniformly assembled with dimensions sized for high frequency applications, including millimeter wave operation.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

A semiconductor device, including a conductive plate having a front surface that includes a plurality of bonding regions and a plurality of non-bonding regions in peripheries of the bonding regions, a plurality of semiconductor elements mounted on the conductive plate in the bonding regions, and a resin encapsulating therein at least the plurality of semiconductor elements and the front surface of the conductive plate. The conductive plate has, at the front surface thereof in the non-bonding regions, a plurality of holes.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

A semiconductor device, including a conductive plate having a front surface that includes a plurality of bonding regions and a plurality of non-bonding regions in peripheries of the bonding regions, a plurality of semiconductor elements mounted on the conductive plate in the bonding regions, and a resin encapsulating therein at least the plurality of semiconductor elements and the front surface of the conductive plate. The conductive plate has, at the front surface thereof in the non-bonding regions, a plurality of holes.

CHIP PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME
20210074682 · 2021-03-11 ·

A package structure and a method of forming the same are provided. The package structure includes a package substrate and an interposer substrate over the package substrate. The interposer substrate has a first surface facing the package substrate and a second surface opposite the first surface. A first semiconductor device is disposed on the first surface, and a second semiconductor device is disposed on the second surface. Conductive structures are disposed between the interposer substrate and the package substrate. The first semiconductor device is located between the conductive structures. A first side of the first semiconductor device is at a first distance from the most adjacent conductive structure, and a second side of the first semiconductor device is at a second distance from the most adjacent conductive structure. The first side is opposite the second side, and the first distance is greater than the second distance.

CHIP PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME
20210074682 · 2021-03-11 ·

A package structure and a method of forming the same are provided. The package structure includes a package substrate and an interposer substrate over the package substrate. The interposer substrate has a first surface facing the package substrate and a second surface opposite the first surface. A first semiconductor device is disposed on the first surface, and a second semiconductor device is disposed on the second surface. Conductive structures are disposed between the interposer substrate and the package substrate. The first semiconductor device is located between the conductive structures. A first side of the first semiconductor device is at a first distance from the most adjacent conductive structure, and a second side of the first semiconductor device is at a second distance from the most adjacent conductive structure. The first side is opposite the second side, and the first distance is greater than the second distance.

PACKAGE AND MANUFACTURING METHOD THEREOF

A package includes a first die, a second die, a first encapsulant, first through insulating vias (TIV), a second encapsulant, and second TIVs. The second die is stacked on the first die. The first encapsulant laterally encapsulates the first die. The first TIVs are aside the first die. The first TIVs penetrate through the first encapsulant and are electrically floating. The second encapsulant laterally encapsulates the second die. The second TIVs are aside the second die. The second TIVs penetrate through the second encapsulant and are electrically floating. The second TIVs are substantially aligned with the first TIVs.

PACKAGE AND MANUFACTURING METHOD THEREOF

A package includes a first die, a second die, a first encapsulant, first through insulating vias (TIV), a second encapsulant, and second TIVs. The second die is stacked on the first die. The first encapsulant laterally encapsulates the first die. The first TIVs are aside the first die. The first TIVs penetrate through the first encapsulant and are electrically floating. The second encapsulant laterally encapsulates the second die. The second TIVs are aside the second die. The second TIVs penetrate through the second encapsulant and are electrically floating. The second TIVs are substantially aligned with the first TIVs.

PACKAGE AND MANUFACTURING METHOD OF RECONSTRUCTED WAFER

A package includes a carrier substrate, a first die, and a second die. The first die includes a first bonding layer, a second bonding layer opposite to the first bonding layer, and an alignment mark embedded in the first bonding layer. The first bonding layer is fusion bonded to the carrier substrate. The second die includes a third bonding layer. The third bonding layer is hybrid bonded to the second bonding layer of the first die.