The present application provides a semiconductor package and a manufacturing method thereof. The semiconductor package includes a package substrate, a bottom device die, a top device die and an additional package substrate. The bottom device die is attached on the package substrate. The top device die is attached on the bottom device die with its active side facing away from the bottom device die. A first portion of die I/Os at the active side of the top device die are electrically connected to the package substrate. The additional package substrate is attached on the active side of the top device die, and electrically connected to the package substrate and a second portion of the die I/Os of the top device die.

The present application provides a semiconductor package and a manufacturing method thereof. The semiconductor package includes a package substrate, a bottom device die, a top device die and an additional package substrate. The bottom device die is attached on the package substrate. The top device die is attached on the bottom device die with its active side facing away from the bottom device die. A first portion of die I/Os at the active side of the top device die are electrically connected to the package substrate. The additional package substrate is attached on the active side of the top device die, and electrically connected to the package substrate and a second portion of the die I/Os of the top device die.

A semiconductor device includes a first plurality of dies encapsulated by an encapsulant, an interposer over the first plurality of dies, an interconnect structure over and electrically connected to the interposer, and a plurality of conductive pads on a surface of the interconnect structure opposite the interposer. The interposer includes a plurality of embedded passive components. Each die of the first plurality of dies is electrically connected to the interposer. The interconnect structure includes a solenoid inductor in a metallization layer of the interconnect structure.

A semiconductor device includes a first plurality of dies encapsulated by an encapsulant, an interposer over the first plurality of dies, an interconnect structure over and electrically connected to the interposer, and a plurality of conductive pads on a surface of the interconnect structure opposite the interposer. The interposer includes a plurality of embedded passive components. Each die of the first plurality of dies is electrically connected to the interposer. The interconnect structure includes a solenoid inductor in a metallization layer of the interconnect structure.

A method for forming a chip package structure is provided. The method includes disposing a chip package over a wiring substrate. The method includes forming a first heat conductive structure and a second heat conductive structure over the chip package. The first heat conductive structure and the second heat conductive structure are separated by a first gap. The method includes bonding a heat dissipation lid to the chip package through the first heat conductive structure and the second heat conductive structure. The first heat conductive structure and the second heat conductive structure extend toward each other until the first heat conductive structure contacts the second heat conductive structure during bonding the heat dissipation lid to the chip package.

A method for forming a chip package structure is provided. The method includes disposing a chip package over a wiring substrate. The method includes forming a first heat conductive structure and a second heat conductive structure over the chip package. The first heat conductive structure and the second heat conductive structure are separated by a first gap. The method includes bonding a heat dissipation lid to the chip package through the first heat conductive structure and the second heat conductive structure. The first heat conductive structure and the second heat conductive structure extend toward each other until the first heat conductive structure contacts the second heat conductive structure during bonding the heat dissipation lid to the chip package.

A package structure includes a circuit element, a first semiconductor die, a second semiconductor die, a heat dissipating element, and an insulating encapsulation. The first semiconductor die and the second semiconductor die are located on the circuit element. The heat dissipating element connects to the first semiconductor die, and the first semiconductor die is between the circuit element and the heat dissipating element, where a sum of a first thickness of the first semiconductor die and a third thickness of the heat dissipating element is substantially equal to a second thickness of the second semiconductor die. The insulating encapsulation encapsulates the first semiconductor die, the second semiconductor die and the heat dissipating element, wherein a surface of the heat dissipating element is substantially leveled with the insulating encapsulation.

A package structure includes a circuit element, a first semiconductor die, a second semiconductor die, a heat dissipating element, and an insulating encapsulation. The first semiconductor die and the second semiconductor die are located on the circuit element. The heat dissipating element connects to the first semiconductor die, and the first semiconductor die is between the circuit element and the heat dissipating element, where a sum of a first thickness of the first semiconductor die and a third thickness of the heat dissipating element is substantially equal to a second thickness of the second semiconductor die. The insulating encapsulation encapsulates the first semiconductor die, the second semiconductor die and the heat dissipating element, wherein a surface of the heat dissipating element is substantially leveled with the insulating encapsulation.

A chip package structure is provided. The chip package structure includes a wiring substrate. The chip package structure includes a chip package over the wiring substrate. The chip package structure includes a first heat conductive structure over the chip package. The chip package structure includes a ring dam over the chip package and surrounding the first heat conductive structure. The ring dam has a gap. The chip package structure includes a heat dissipation lid over the first heat conductive structure and the ring dam.

A chip package structure is provided. The chip package structure includes a wiring substrate. The chip package structure includes a chip package over the wiring substrate. The chip package structure includes a first heat conductive structure over the chip package. The chip package structure includes a ring dam over the chip package and surrounding the first heat conductive structure. The ring dam has a gap. The chip package structure includes a heat dissipation lid over the first heat conductive structure and the ring dam.