A semiconductor package includes a package substrate; a plurality of lower chip structures on the package substrate; an upper chip structure on the plurality of lower chip structures and covering portions of upper surfaces of the plurality of lower chip structures; a non-conductive adhesive layer on a lower surface of the upper chip structure and receiving upper portions of the plurality of lower chip structures; and a molded member on the plurality of lower chip structures and the upper chip structure.

A semiconductor package includes a package substrate; a plurality of lower chip structures on the package substrate; an upper chip structure on the plurality of lower chip structures and covering portions of upper surfaces of the plurality of lower chip structures; a non-conductive adhesive layer on a lower surface of the upper chip structure and receiving upper portions of the plurality of lower chip structures; and a molded member on the plurality of lower chip structures and the upper chip structure.

The present invention pertains to a curable organopolysiloxane composition comprising at least (A) an organopolysiloxane having at least two alkenyl groups per module, (B) an organopolysiloxane resin represented by average unit formula: (R.sup.1.sub.3SiO.sub.1/2).sub.a(R.sup.1.sub.2SiO.sub.2/2).sub.b(R.sup.2SiO.sub.3/2).sub.c(SiO.sub.4/2).sub.d. In the formula, R.sup.1's are the same or different from each other, and represent a hydrogen atom or a monovalent hydrocarbon group not having an aliphatic unsaturated carbon bond but at least two of the R.sup.1's per molecule represent hydrogen atoms, R.sup.2 represents a monovalent hydrocarbon group not having an aliphatic unsaturated bond, and a, b, and c are numbers satisfying 0<a<1, 0<b<1, and 0c0.2, and 0<d<1, respectively, but are also numbers satisfying 0.6a/d 1.5, 1.5b/d3, and a+b+c+d=1, and (C) a catalyst for hydrosilylation reaction. This composition has excellent adhesiveness to a semiconductor element, and can form a cured product in which only a small number of bubbles are produced.

The present invention pertains to a curable organopolysiloxane composition comprising at least (A) an organopolysiloxane having at least two alkenyl groups per module, (B) an organopolysiloxane resin represented by average unit formula: (R.sup.1.sub.3SiO.sub.1/2).sub.a(R.sup.1.sub.2SiO.sub.2/2).sub.b(R.sup.2SiO.sub.3/2).sub.c(SiO.sub.4/2).sub.d. In the formula, R.sup.1's are the same or different from each other, and represent a hydrogen atom or a monovalent hydrocarbon group not having an aliphatic unsaturated carbon bond but at least two of the R.sup.1's per molecule represent hydrogen atoms, R.sup.2 represents a monovalent hydrocarbon group not having an aliphatic unsaturated bond, and a, b, and c are numbers satisfying 0<a<1, 0<b<1, and 0c0.2, and 0<d<1, respectively, but are also numbers satisfying 0.6a/d 1.5, 1.5b/d3, and a+b+c+d=1, and (C) a catalyst for hydrosilylation reaction. This composition has excellent adhesiveness to a semiconductor element, and can form a cured product in which only a small number of bubbles are produced.

A micro LED display manufacturing method according to various embodiments may include: a first operation of bonding an anisotropic conductive film including a plurality of conductive particles onto one surface of a prepared substrate, the one surface including a circuit part; a second operation of forming a bonding layer on the anisotropic conductive film; a third operation of positioning a plurality of micro LED chips above the bonding layer, the micro LED chips being arranged on a carrier substrate while being spaced a first distance apart from the substrate; a fourth operation of attaching the plurality of micro LED chips onto the bonding layer by means of laser transfer; and a fifth operation of forming a conductive structure for electrically connecting a connection pad to the circuit part through the conductive particles by means of heating and pressurizing.

A micro LED display manufacturing method according to various embodiments may include: a first operation of bonding an anisotropic conductive film including a plurality of conductive particles onto one surface of a prepared substrate, the one surface including a circuit part; a second operation of forming a bonding layer on the anisotropic conductive film; a third operation of positioning a plurality of micro LED chips above the bonding layer, the micro LED chips being arranged on a carrier substrate while being spaced a first distance apart from the substrate; a fourth operation of attaching the plurality of micro LED chips onto the bonding layer by means of laser transfer; and a fifth operation of forming a conductive structure for electrically connecting a connection pad to the circuit part through the conductive particles by means of heating and pressurizing.

A semiconductor package structure including a circuit substrate, a redistribution layer, and at least two dies is provided. The circuit substrate has a first surface and a second surface opposite the first surface. The redistribution layer is located on the first surface. The redistribution layer is electrically connected to the circuit substrate. The spacing of the opposing sidewalls of the redistribution layer is less than the spacing of the opposing sidewalls of the circuit substrate. The redistribution layer is directly in contact with the circuit substrate. At least two dies are disposed on the redistribution layer. Each of the at least two dies has an active surface facing the circuit substrate. One of the at least two dies is electrically connected to the other of the at least two dies by the redistribution layer. A manufacturing method of a semiconductor package structure is also provided.

A semiconductor package structure including a circuit substrate, a redistribution layer, and at least two dies is provided. The circuit substrate has a first surface and a second surface opposite the first surface. The redistribution layer is located on the first surface. The redistribution layer is electrically connected to the circuit substrate. The spacing of the opposing sidewalls of the redistribution layer is less than the spacing of the opposing sidewalls of the circuit substrate. The redistribution layer is directly in contact with the circuit substrate. At least two dies are disposed on the redistribution layer. Each of the at least two dies has an active surface facing the circuit substrate. One of the at least two dies is electrically connected to the other of the at least two dies by the redistribution layer. A manufacturing method of a semiconductor package structure is also provided.

A package structure includes a circuit element, a first semiconductor die, a second semiconductor die, a heat dissipating element, and an insulating encapsulation. The first semiconductor die and the second semiconductor die are located on the circuit element. The heat dissipating element connects to the first semiconductor die, and the first semiconductor die is between the circuit element and the heat dissipating element, where a sum of a first thickness of the first semiconductor die and a third thickness of the heat dissipating element is substantially equal to a second thickness of the second semiconductor die. The insulating encapsulation encapsulates the first semiconductor die, the second semiconductor die and the heat dissipating element, wherein a surface of the heat dissipating element is substantially leveled with the insulating encapsulation.

A package structure includes a circuit element, a first semiconductor die, a second semiconductor die, a heat dissipating element, and an insulating encapsulation. The first semiconductor die and the second semiconductor die are located on the circuit element. The heat dissipating element connects to the first semiconductor die, and the first semiconductor die is between the circuit element and the heat dissipating element, where a sum of a first thickness of the first semiconductor die and a third thickness of the heat dissipating element is substantially equal to a second thickness of the second semiconductor die. The insulating encapsulation encapsulates the first semiconductor die, the second semiconductor die and the heat dissipating element, wherein a surface of the heat dissipating element is substantially leveled with the insulating encapsulation.