A method for forming a semiconductor structure includes following operations. A first substrate including a first side, a second side opposite to the first side, and a metallic pad disposed over the first side is received. A dielectric structure including a first trench directly above the metallic pad is formed. A second trench is formed in the dielectric structure and a portion of the first substrate. A sacrificial layer is formed to fill the first trench and the second trench. A third trench is formed directly above the metallic pad. A barrier ring and a bonding structure are formed in the third trench. A bonding layer is disposed to bond the first substrate to a second substrate. A portion of the second side of the first substrate is removed to expose the sacrificial layer. The sacrificial layer is removed by an etchant.

RF transistor amplifiers include an RF transistor amplifier die having a Group III nitride-based semiconductor layer structure and a plurality of gate terminals, a plurality of drain terminals, and at least one source terminal that are each on an upper surface of the semiconductor layer structure, an interconnect structure on an upper surface of the RF transistor amplifier die, and a coupling element between the RF transistor amplifier die and the interconnect structure that electrically connects the gate terminals, the drain terminals and the source terminal to the interconnect structure.

RF transistor amplifiers include an RF transistor amplifier die having a Group III nitride-based semiconductor layer structure and a plurality of gate terminals, a plurality of drain terminals, and at least one source terminal that are each on an upper surface of the semiconductor layer structure, an interconnect structure on an upper surface of the RF transistor amplifier die, and a coupling element between the RF transistor amplifier die and the interconnect structure that electrically connects the gate terminals, the drain terminals and the source terminal to the interconnect structure.

Liquid metal thermal interface materials and their uses in electronics assembly are described. In one implementation, a semiconductor assembly includes: a semiconductor die; a heat exchanger; and a thermal interface material (TIM) alloy bonding the semiconductor die to the heat exchanger without using a separate metallization layer on a surface of the semiconductor die or a surface of the heat exchanger. The TIM alloy may be formed by placing a TIM material between the semiconductor die and the heat exchanger, the TIM material comprising a first liquid metal foam in touching relation with the surface of the semiconductor die, a second liquid metal foam in touching relation with the surface of the heat exchanger.

An electronic device comprises a target substrate, a micro semiconductor structure array, a conductor array, and a connection layer. The micro semiconductor structure array is disposed on the target substrate. The conductor array corresponds to the micro semiconductor structure array, and electrically connects the micro semiconductor structure array to a pattern circuit of the target substrate. The conductors of the conductor array are independent from one another. Each conductor is an integrated member formed by eutectic bonding a conductive pad of the target substrate and a conductive electrode of the corresponding one of the micro semiconductor structures of the micro semiconductor structure array. The connection layer connects the micro semiconductor structures to the target substrate. The connection layer excludes a conductive material. The connection layer contacts and surrounds the conductors, so that the connection layer and the conductors together form a one-layer structure.

A method of removing a substrate, comprising: forming a growth restrict mask with a plurality of striped opening areas directly or indirectly upon a GaN-based substrate; and growing a plurality of semiconductor layers upon the GaN-based substrate using the growth restrict mask, such that the growth extends in a direction parallel to the striped opening areas of the growth restrict mask, and growth is stopped before the semiconductor layers coalesce, thereby resulting in island-like semiconductor layers. A device is processed for each of the island-like semiconductor layers. Etching is performed until at least a part of the growth restrict mask is exposed. The devices are then bonded to a support substrate. The GaN-based substrate is removed from the devices by a wet etching technique that at least partially dissolves the growth restrict mask. The GaN substrate that is removed then can be recycled.

A manufacturing method fora micro light-emitting diode (LED) display panel includes: providing a base substrate carrying a plurality of LED dies, each LED die including a first semiconductor layer, a light-emitting material layer, a second semiconductor layer and a first conductive layer, the first semiconductor layer being bonded with the base substrate through a sacrificial layer, a material of the sacrificial layer being decomposable under laser irradiation; providing a backplane having a plurality of bonding structures; bonding at least some LED dies of the plurality of LED dies to at least some of the plurality of bonding structures through respective first conductive layers; and peeling each of the at least some LED dies from the base substrate through laser lift-off.

A manufacturing method fora micro light-emitting diode (LED) display panel includes: providing a base substrate carrying a plurality of LED dies, each LED die including a first semiconductor layer, a light-emitting material layer, a second semiconductor layer and a first conductive layer, the first semiconductor layer being bonded with the base substrate through a sacrificial layer, a material of the sacrificial layer being decomposable under laser irradiation; providing a backplane having a plurality of bonding structures; bonding at least some LED dies of the plurality of LED dies to at least some of the plurality of bonding structures through respective first conductive layers; and peeling each of the at least some LED dies from the base substrate through laser lift-off.

The present disclosure relates to a semiconductor chip that includes a substrate, a metal layer, and a number of component portions. Herein, the substrate has a substrate base and a number of protrusions protruding from a bottom surface of the substrate base. The substrate base and the protrusions are formed of a same material. Each of the protrusions has a same height. At least one via hole extends vertically through one protrusion and the substrate base. The metal layer selectively covers exposed surfaces at a backside of the substrate and fully covers inner surfaces of the at least one via hole. The component portions reside over a top surface of the substrate base, such that a certain one of the component portions is electrically coupled to a portion of the metal layer at the top of the at least one via hole.

The present disclosure relates to a semiconductor chip that includes a substrate, a metal layer, and a number of component portions. Herein, the substrate has a substrate base and a number of protrusions protruding from a bottom surface of the substrate base. The substrate base and the protrusions are formed of a same material. Each of the protrusions has a same height. At least one via hole extends vertically through one protrusion and the substrate base. The metal layer selectively covers exposed surfaces at a backside of the substrate and fully covers inner surfaces of the at least one via hole. The component portions reside over a top surface of the substrate base, such that a certain one of the component portions is electrically coupled to a portion of the metal layer at the top of the at least one via hole.