A semiconductor device includes a semiconductor die with a metallization layer including a first metal with a comparatively high melting point, a die carrier including a second metal with a comparatively high melting point, a first intermetallic compound arranged between the semiconductor die and the die carrier and including the first metal and a third metal with a comparatively low melting point, a second intermetallic compound arranged between the first intermetallic compound and the die carrier and including the second metal and the third metal, and precipitates of a third intermetallic compound arranged between the first intermetallic compound and the second intermetallic compound and including the third metal and a fourth metal with a comparatively high melting point.

A semiconductor package includes a power semiconductor chip comprising SiC, a leadframe part comprising Cu, wherein the power semiconductor chip is arranged on the leadframe part, and a solder joint electrically and mechanically coupling the power semiconductor chip to the leadframe part, wherein the solder joint comprises at least one intermetallic phase.

A method of forming an interconnection includes: providing an electronic component having a first main face and a first metallic layer disposed on the first main face; providing an electric component having a second main face and a second metallic layer disposed on the second main face, at least one of the first or second metallic layers including an oxide layer provided on a main face thereof; disposing a reducing agent on one or both of the electronic component and the electric component such that the reducing agent is enabled to remove the oxide layer; and connecting the electronic component to the electric component by directly connecting the first metallic layer of the electronic component with the second metallic layer of the electric component by applying pressure and heat.

A solder joint in which an electronic component with a back metal is bonded to a substrate by a solder alloy. The solder alloy includes: a solder alloy layer having an alloy composition consisting of, in mass %: Ag: 2 to 4%, Cu: 0.6 to 2%, Sb: 9.0 to 12%, Ni: 0.005 to 1%, optionally Co: 0.2% or less and Fe: 0.1% or less, with the balance being Sn; an Sn—Sb intermetallic compound phase; a back metal-side intermetallic compound layer formed at an interface between the back metal and the solder alloy; and a substrate-side intermetallic compound layer formed at an interface between the substrate and the solder alloy. The solder alloy layer exists at least one of between the Sn—Sb intermetallic compound phase and the back metal-side intermetallic compound layer, and between the Sn—Sb intermetallic compound phase and the substrate-side intermetallic compound layer.

The present invention provides a highly reliable solder joint, the solder joint including a solder joint layer having a melted solder material containing Sn as a main component and further containing Ag and/or Sb and/or Cu; and a joined body including a Ni—P—Cu plating layer on a surface in contact with the solder joint layer, wherein the Ni—P—Cu plating layer contains Ni as a main component and contains 0.5% by mass or greater and 8% by mass or less of Cu and 3% by mass or greater and 10% by mass or less of P, the Ni—P—Cu plating layer has a microcrystalline layer at an interface with the solder joint layer, and the microcrystalline layer includes a phase containing microcrystals of a NiCuP ternary alloy, a phase containing microcrystals of (Ni,Cu).sub.3P, and a phase containing microcrystals of Ni.sub.3P.

A method of joining a semiconductor die to a substrate includes: applying a solder preform to a metal region of the semiconductor die or to a metal region of the substrate, the solder preform having a maximum thickness of 30 μm and a lower melting point than both metal regions; forming a soldered joint between the metal region of the semiconductor die and the metal region of the substrate via a diffusion soldering process and without applying pressure directly to the die; and setting a soldering temperature of the diffusion soldering process so that the solder preform melts and fully reacts with the metal region of the semiconductor die and the metal region of the substrate to form one or more intermetallic phases throughout the entire soldered joint, each intermetallic phase having a melting point above the melting point of the preform and the soldering temperature.

A method of batch soldering includes: forming a soldered joint between a metal region of a first semiconductor die and a metal region of a substrate using a solder preform via a soldering process which does not apply pressure directly to the first semiconductor die, the solder preform having a maximum thickness of 30 μm and a lower melting point than the metal regions; setting a soldering temperature of the soldering process so that the solder preform melts and fully reacts with the metal region of the first semiconductor die and the metal region of the substrate to form one or more intermetallic phases throughout the entire soldered joint, each intermetallic phase having a melting point above the preform melting point and the soldering temperature; and soldering a second semiconductor die to the same or different metal region of the substrate, without applying pressure directly to the second semiconductor die.

A method of forming a solar cell device that includes forming a porous layer in a monocrystalline donor substrate and forming an epitaxial semiconductor layer on the porous layer. A solar cell structure is formed on the epitaxial semiconductor layer. A carrier substrate is bonded to the solar cell structure through a bonding layer. The monocrystalline donor substrate is removed by cleaving the porous layer. A grid of metal contacts is formed on the epitaxial semiconductor layer. The exposed portions of the epitaxial semiconductor layer are removed. The exposed surface of the solar cell structure is textured. The textured surface may be passivated, in which the passivated surface can provide an anti-reflective coating.

A display panel and method of manufacture are described. In an embodiment, a display substrate includes a pixel area and a non-pixel area. An array of subpixels and corresponding array of bottom electrodes are in the pixel area. An array of micro LED devices are bonded to the array of bottom electrodes. One or more top electrode layers are formed in electrical contact with the array of micro LED devices. In one embodiment a redundant pair of micro LED devices are bonded to the array of bottom electrodes. In one embodiment, the array of micro LED devices are imaged to detect irregularities.

The present disclosure provides a method of creating a bond between a first object and a second object. For example, creating a joint or die attach between a semiconductor chip and an electronic substrate, especially for harsh and high temperature environments. The method may include a step of filling a space between the first object and the second object with a filler material. Further, the method may include a step of heating the filler material to facilitate formation of a plurality of inter-diffusion layers. Accordingly, a first inter-diffusion layer may be formed between the filler material and the first object. Further, a second inter-diffusion layer may be formed between the filler material and the second object. Furthermore, in some embodiments, the first inter-diffusion layer may be contiguous with the second inter-diffusion layer. The contiguity may be facilitated by placement of at least one insert between the first object and the second object, in which the inter-diffusion of the filler material and the at least one insert may produce the third inter-diffusion layer, wherein the third inter-diffusion layer is contiguous with each of the first inter-diffusion layer and the second inter-diffusion layer.