The present invention relates to a reel-to-reel layer reflow method, which emits a uniformized laser beam, which can easily adjust the emission area, and which is for the purpose of improving productivity. An embodiment of the present invention provides a reel-to-reel layer reflow method comprising the steps of: a) transferring a substrate, which has been wound in a roll type, to one side while unwinding the same; b) forming a solder portion on the substrate; c) seating an emission target element on the solder portion and seating a non-emission target element on the substrate; d) surface-emitting a laser beam to the solder portion, on which the emission target element is seated, such that the emission target element is attached to the substrate; e) inspecting the substrate structure manufactured through said step d); and f) winding the substrate structure in a roll type.

The invention refers to a method for assembling at least one lighting element onto a substrate, the method comprising: pre-assembling at least one lighting element onto a temporary carrier; pre-assembling at least one reference element onto the temporary carrier; aligning the pre-assembled temporary carrier onto the substrate based, at least in part, on the at least one reference element of the temporary carrier; and mounting the at least one lighting element onto the substrate. The invention further relates to substrate comprising: at least one lighting element, wherein the at least one lighting element is assembled onto the substrate, in particular by a method according to the first aspect of the present invention, and to a use of a method for assembling at least one lighting element onto a substrate.

A packaged electronic device includes a stacked configuration of a first semiconductor die in a first recess in a first side of a first conductive plate, a second semiconductor die in a second recess in a first side of a second conductive plate, a third conductive plate electrically coupled to a second side of the second semiconductor die, and a package structure that encloses the first semiconductor die, and the second semiconductor die, where the package structure includes a side that exposes a portion of a second side of the first conductive plate.

A semiconductor device includes a die pad, a semiconductor element, a joining layer, a first conductive member, and a second conductive member. The semiconductor element has a first electrode opposing an obverse surface of the die pad, and a second electrode and a third electrode that are opposite to the first electrode in a thickness direction. The first electrode is electrically joined to the obverse surface. The joining layer electrically joins the first electrode and the obverse surface to each other. The first conductive member is electrically joined to the second electrode. The second conductive member is electrically joined to the third electrode. The area of the third electrode is smaller than the area of the second electrode as viewed along the thickness direction. The Young's modulus of the second conductive member is smaller than the Young's modulus of the first conductive member.

A pressure collet that operably engages with a die in which the pressure collet is configured to land on predetermined positions of the die without damaging said die, a perform, or a heat spreader during a reflow process. The pressure collet further comprises a plate that has a mounting surface and a plurality of contact pads that operably engages with the mounting surface of the plate. The plurality of contact pads is configured to apply pressure to predetermined positions of a die without the mounting surface of the plate contacting the die during a reflow process. The plate of the pressure collet is also formed of a first material and the plurality of contact pads are formed of a second material different than the first material.

A semiconductor package includes a lead frame, a semiconductor chip, a plurality of three-dimensional wrings, and a mold resin. The semiconductor chip is mounted on the lead frame. The mold resin covers a part of the lead frame, the semiconductor chip, and a part of each of the plurality of three-dimensional wirings.

A semiconductor package includes a lead frame, a semiconductor chip, a plurality of three-dimensional wrings, and a mold resin. The semiconductor chip is mounted on the lead frame. The mold resin covers a part of the lead frame, the semiconductor chip, and a part of each of the plurality of three-dimensional wirings.

A power module according implementations of the present disclosure includes a bonding layer for bonding two adjacent members. The bonding layer is formed by melting, applying, and solidifying a bonding material that has excellent thermal conductivity and electrical conductivity. The melted bonding material includes a plurality of anti-tilting members. The two members bonded during the process of solidifying the melted bonding material are supported by the plurality of anti-tilting members. This may allow tilting caused during the formation of the bonding layer to be suppressed.

A printed circuit film includes: a base film including a first film portion extending in a first direction, a second film portion extending in the first direction, and a third film portion extending in the first direction; a plurality of lead wires extending in the second direction and disposed on the first, second, and third film portions, the plurality of lead wires being spaced apart from each other in the first direction; and a bonding member including: a conductive member disposed to overlap the plurality of lead wires on the first film portion; a first non-conductive member disposed to overlap the plurality of lead wires and the second film portion; and a second non-conductive member disposed to overlap the plurality of lead wires and the third film portion, wherein the conductive member is disposed between the first non-conductive member and the second non-conductive member in the second direction.

A chip structure includes a substrate, a bottom conductive layer, a semiconductor layer, an interlayer dielectric layer, at least one electrode, and at least one top electrode. The substrate includes in order a core layer and a composite material. The bottom conductive layer is disposed on the bottom surface of the core layer, the semiconductor layer is disposed on the substrate, and an interlayer dielectric layer is disposed on the semiconductor layer. The at least one electrode is disposed between the semiconductor layer and the interlayer dielectric layer, and the at least one top electrode is disposed on the interlayer dielectric layer and electrically coupled to the at least one electrode.